AFE7950EVM: PLL loop 1 not locking with valid external source

Part Number: AFE7950EVM

Dear TI

I am using the AFE7950-TRF1208 EVM Evaluation module. I have a 10MHz source on the LMK_CLK_IN connector.

As per the document SBAU392, both LEDs D3 and D4 should be lit. In this case only the PLL 2 LED (D3) is lit, not D4. 

I have checked the LMK Clock Divider settings in the Latte Device List. R = 125 and N = 1536 which should mean that PLL 1 is locked with 10MHz input on CLKIN1.

Can you please provide some assistance? 

Regards

Khusro