Other Parts Discussed in Thread: AFE7950EVM
Hello,
1) In the ADC interface (STX) there are 3 differential pairs that are polarity inverted but in the code the inversion is for 4 pairs
2) May I ask you to please help us understand the syntax for polarity inversion?
3) In the Vivado code, the received and transmit data is rx_lane_data and tx_lane_data. Like before is this data synchronous to mgt_rx_usrclk2? Is this now at (122.88 x 2 = 245.76 MHz) ? Since we are using RxA and RxC, the corresponding lines will be rx_lane_data[0], rx_lane_data[1] for RxA and rx_lane_data[4] and rx_lane_data[5] for RxC. For TxB it will tx_lane_data[2], tx_lane_data[3] and TxD it will be tx_lane_data[6] and tx_lane_data[7].
4) Are sys_clk and refclk at 122.88MHz (as per the comments in the constraint file it is 156.25MHz but the timing constraint and the PLL setting itself is for 122.88MHz)?
5) Please advise on how to achieve deterministic latency and what is the number for this (the latency between channels rxA + txB and rxC + txD? Please advise on your measurement setup for the same. Is there a separate sync pin needed for this or sysref takes care of it?
6) We have two setups: one with AFE7900EVM and the other with AFE7950EVM. In the AFE7950EVM I think all the channels are identical so the front end for 42220 doesn't need to be modified and we will be using it for testing at 10GHz.
Please advise on the changes needed for AFE7900EVM for testing in the following bands:
1) 3.5 to 4.5GHz
2) 5GHz
7) Since we need to set the Tx and Rx NCO frequencies ourselves please advise on how to calculate the register values for different NCO values. I assume these are independent of the mode (42220 or any other mode where the DAC and ADC sampling frequencies remain the same).
Thanks,
