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Original question:

AFE7900: Query Regarding the Rx output FFT given in AFE7900 datasheet

AFE7900: Is there any difference between 1-link 2-lane and 2-link 1-lane configuration?

Links
Intellectual 2465 points
Part Number: AFE7900

Dear team,

our customer has a inquiry below

I want to communicate with AFE7900 in Xilinx FPGA. I need to design SERDERS Rate is 10 Gbps, and the output rates are 125 MSPS. I got some information about JESD204B configuration in device datasheet. AFE7900

SBASA43A – AUGUST 2021 – REVISED JULY 2022 PAGE - 202 
Table 8-15. JESD204B/C Formats for 1 DDC per RX Chain (4 RX)
 
However, the device has 2 different configuration in desired parameters. I searched these configuration parameters but I did not get any details about difference between these two configurations. 
 
Could you share to me the differences?  
 
Second question, if I want to work with 2-link 1-lane configuration, can the design only work with 1-Xilinx JESD204B IP? Or should I design with 2-Xilinx JESD204B IP? Another word, in figure 1, there are two axis_data[31:0] signals, [assume that these are concatenated], in figure two there is one axis_data[63:0] signal. On the application side, are the two axis_data in Figure 1 and Figure 2 the same? 
 
rx_chain-Page-2

Best regards,
William
  • 0
    TI__Genius 10685 points

    Hi William,

    For 125MSPS data rate and 10Gbps SERDES rate, the AFE JESD can be configured as single link for all 4 converters (LMFS: 2-8-8-1-0) or two links with 2 converters each (LMFS: 1-4-8-1-0 each). Using it in single link mode is less complex as there will be only one JESD SYNC signal connecting FPGA to AFE. Only one instance of JESD IP is needed on the FPGA. 

    If two link mode is used, two separate JESD sync signals have to be connected from FPGA to AFE. Because of this, two instances of JESD IP are needed on FPGA.

    Advantage of using two links is that incase there are errors on only one of the two lanes, only that one link would go down and have to re-sync. But if both lanes are combined to one link, errors on any one lane would bring down the JESD link for both lanes. 

    If you have access to AFE secure folder, please refer to the example JESD reference designs for AFE79xxEVM with Xilinx dev kits. These reference designs use TI JESD IP (https://www.ti.com/tool/TI-JESD204-IP). These proven design are good starting point for developing custom JESD designs for AFE79xx. 

    Regards,

    Vijay