Original question:
Part Number: AFE7950EVM
Can AFE7950EVM run on Xilinx ZC706?
I want to develop program with LabVIEW and VIVADO. And I have get the TI-JESD204-IP but don't know how to start.
Can TI provide libraries and usages?
hi David，
I am chaoyang's colleague. What's the secure folder you mentioned? We acquired the AFE7950 data and it looks like
I did not see any file about zc706. Should I acquire another?
Hi David,
Thanks for your reply. The error is fixed.
I have some more questions.
1.What is available number of Number of Samples/Channel in ILA Analyser?
2.How to receive all 6 ADC channel data(4 RX/2 FB)?
What parameters should be modified?
Hi Chaoyang,
The AFE79xx device only has 8 STX lanes that can be used by both the Rx and Fb channels. This means that the AFE79xx configuration must be updated so that the 8 lanes are shared between the Rx and Fb channels. One way to do this is to update the Rx LMFS mode to 24410 and the Fb LMFS to 12410. This will configure the Rx and Fb channels to use a total of 6 lanes. Then you can update the jesd_link_params, refdesign_rx, and transceiver IP to use the 6 lanes. For the refdesign_rx file the data unpacking would need to be updated for the Rx and Fb because now that the LMFS is 24410 or 12410 the data format will now be:
The Latte script that is configured for the mode I mentioned is below.
############## Read me ##############
#In HSDC Pro DAC tab, Select AFE79xx_2x2TX_44210; Data Rate = 491.52M
#In HSDC Pro ADC tab, Select AFE79xx_2x2RX_24410; Data Rate = 245.76M ---> To capture 4 RX channels
#In HSDC Pro ADC tab, Select AFE79xx_1x2FB_44210; Data Rate = 491.52M ---> To capture 2 FB channels
sysParams=AFE.systemParams
sysParams.__init__();sysParams.chipVersion=chipVersion
setupParams.skipFpga = 1 # setup FPGA (TSW14J56) using HSDC Pro
############## Top Level ##############
sysParams.FRef = 491.52
sysParams.FadcRx = 2949.12
sysParams.FadcFb = 2949.12
sysParams.Fdac = 2949.12*4
sysParams.externalClockRx=False
sysParams.externalClockTx=False
############## Digital Chain ##############
##### RX #####
sysParams.ddcFactorRx = [12,12,12,12] #DDC decimation factor for RX A, B, C and D
sysParams.rxNco0 = [[5400,5400], #Band0, Band1 for RXA
[500,500], #Band0, Band1 for RXB
[2500,2500], #Band0, Band1 for RXC
[1800,1800]] #Band0, Band1 for RXD
##### FB #####
sysParams.ddcFactorFb = [12,12] #DDC decimation factor for FB 1 and 2
sysParams.fbNco0 = [500,1800] #Band0 for FB1 and FB2
##### TX #####
sysParams.ducFactorTx = [24,24,24,24] #DUC interpolation factor for TX A, B, C and D
sysParams.txNco0 = [[5400,5400], #Band0, Band1 for TXA
[500,500], #Band0, Band1 for TXB
[2600,2500], #Band0, Band1 for TXC
[1800,1800]] #Band0, Band1 for TXD
############## JESD ##############
##### ADC-JESD #####
sysParams.jesdSystemMode= [1,1]
#SystemMode 0: 2R1F-FDD ; rx1-rx2-fb -fb
#SystemMode 1: 1R1F-FDD ; rx -rx -fb -fb
#SystemMode 2: 2R-FDD ; rx1-rx1-rx2-rx2
#SystemMode 3: 1R ; rx -rx -rx -rx
#SystemMode 4: 1F ; fb -fb- fb -fb
#SystemMode 5: 1R1F-TDD ; rx/fb-rx/fb-rx/fb-rx/fb
sysParams.jesdTxProtocol= [0,0] # 0 - 8b/10b encoding; 2 - 64b/66b encoding
sysParams.LMFSHdRx = ["24410","24410","24410","24410"]
# The 2nd and 4th are valid only for jesdSystemMode values in (0,2).
# For other modes, select 4 converter modes for 1st and 3rd.
sysParams.LMFSHdFb = ["12410","12410"]
sysParams.rxJesdTxScr = [True,True,True,True]
sysParams.fbJesdTxScr = [True,True]
sysParams.rxJesdTxK = [32,32,32,32]
sysParams.fbJesdTxK = [32,32]
sysParams.jesdTxLaneMux = [0,1,2,3,4,5,6,7] # Enter which lanes you want in each location.
# For example, if you want to exchange the first two lines of each 2T,
# this should be [[1,0,2,3],[5,4,6,7]]
##### DAC-JESD #####
sysParams.jesdRxProtocol= [0,0]
sysParams.LMFSHdTx = ["44210","44210","44210","44210"]
sysParams.jesdRxLaneMux = [0,1,2,3,4,5,6,7] # Enter which lanes you want in each location.
# For example, if you want to exchange the first two lines of each 2R
# this should be [[1,0,2,3],[5,4,6,7]]
sysParams.jesdRxRbd = [4, 4]
sysParams.jesdRxScr = [True,True,True,True]
sysParams.jesdRxK = [32,32,32,32]
##### JESD Common #####
sysParams.jesdABLvdsSync= False
sysParams.jesdCDLvdsSync= False
sysParams.syncLoopBack = True #JESD Sync signal is connected to FPGA
############## GPIO ##############
sysParams.gpioMapping = {
'H8': 'ADC_SYNC0',
'H7': 'DAC_SYNC0',
'N8': 'ADC_SYNC2',
'N7': 'ADC_SYNC3',
'H9': 'ADC_SYNC1',
'G9': 'DAC_SYNC1',
'N9': 'DAC_SYNC2',
'P9': 'DAC_SYNC3',
'P14': 'GLOBAL_PDN',
'K14': 'FBABTDD',
'R6': 'FBCDTDD',
'H15': ['TXATDD','TXBTDD'],
'V5': ['TXCTDD','TXDTDD'],
'E7': ['RXATDD','RXBTDD'],
'R15': ['RXCTDD','RXDTDD']}
############## LMK Params ##############
lmkParams.pllEn = True
lmkParams.inputClk = 983.04 # Valid only when lmkParams.pllEn = False
lmkParams.lmkFrefClk = True
setupParams.fpgaRefClk = 122.88 # Should be equal to LaneRate/40 for TSW14J56
############## Logging ##############
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat=0x0 #Modify to 0x1 to save register scequence to log file. Script takes more time to execute.
logDumpInst.rewriteFile=1
logDumpInst.rewriteFileFormat4=1
device.optimizeWrites=0
device.rawWriteLogEn=1
device.delay_time = 0
#-------------------------------------------------------------------------------------------------#
setupParams.skipLmk = False
AFE.initializeConfig()
lmkParams.sysrefFreq = AFE.systemStatus.sysrefFreq
lmkParams.lmkPulseSysrefMode = False
AFE.LMK.lmkConfig()
Regards,
David Chaparro
Hi David,
I modify the code as following pic
jesd_link_params.vh:
TI_204c_IP_ref.sv:
refdesign_rx.sv:
Then, I get error in vivado.
What else need to be modified?
Hi David,
I didn't get the Fb1/2 on ila waveform and the max adc value of rxa\b\c\d are different.
I set all rx/fb NCO as 2000 and connect the same 2.1GHz signal to all ch.
What else need to be modified?
rxa
rxb
rxc
rxd
