• State TI Thinks Resolved
  • Locked Locked
  • Replies 6 replies
  • Answers 3 answers
  • Subscribers 10 subscribers
  • Views 1049 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AFE7900: AFE7900 SyncIN and SyncOut

TOLGA KELES
Prodigy 40 points
Part Number: AFE7900

Hello,

The configuration I am using is as follows:

LMFSHdTx[14810] and LMFSHdRx [181610] 

SYNC_IN connect LVDS and H8 and H7 pins. (SYNC_IN0)

SYNC_IN1 (N8 and N7) pins not connected.

SYNC_OUT connect LVDS and N9 and P9 pins. (SYNC_OUT1)

SYNC_OUT0 (H9 and G9) pins not connected.

GPIO Pins connect GPIO1….GPIO6.

But, I couldn't get the sync signals to work. The latte bring up file is as follows:

## The following parameters sets up the SYNCIN and SYNCOUT to interface with the TSW14J57
sysParams.jesdABLvdsSync = 1
sysParams.jesdCDLvdsSync = 1
sysParams.rxJesdTxSyncMux = [0,0,0,0]
sysParams.fbJesdTxSyncMux = [0,0]
sysParams.jesdRxSyncMux = [0,0,0,0] #[0,0,1,1]
sysParams.syncLoopBack = True

How should I set this place so that the sync signals work from the pins I specified?

Thank you,

  • 0
    Prodigy 40 points

    Is there anyone who can answer this question I asked?

  • 0 in reply to TOLGA KELES
    TI__Genius 17671 points

    Hi Tolga,

    The SYNC settings that you show above are correct. The issue that you most likely facing is caused by the pin assignment in the gpioMapping parameter. To use pins H8 and H7 for ADC Sync and N9 and P9 for DAC Sync the gpioMapping should look like below

    Regards,

    David Chaparro

  • 0 in reply to David Chaparro
    Prodigy 40 points

    Hi David,

    Thank you very much for your reply. I have additional questions for you. 

    We fixed the configuration we used as follows. We thought we needed to fix the Sync mux order. (We could not fully understand how we should set these syncs from the configuration datasheet.)
    Do we need 2 sync signals for both rx and tx for this configuration? (I said at the beginning of my question which sync signals and gpio signals are available on my card)

    LMFSHdTx[14810] and LMFSHdRx [181610]
    sysParams.jesdABLvdsSync = 0
    sysParams.jesdCDLvdsSync = 0
    sysParams.rxJesdTxSyncMux = [0,0,1,1]
    sysParams.jesdRxSyncMux = [2,2,3,3]

  • 0 in reply to TOLGA KELES
    TI__Genius 17671 points

    Hi Tolga,

    Only a single sync signal is required for Rx and one on sync is required for Tx. The settings I showed in my previous response is setting the first sync for both ADC and DAC to the pins outlined in your question. The settings below show the correct pin assignment for your pins.

    Regards,

    David Chaparro

  • 0 in reply to David Chaparro
    Prodigy 40 points

    Hi David,

    Thank you your answer. Your answer has created some other questions in my mind. 

    I couldn't understand the relation between Lane number - using Sync number.

    Also, when we load this configuration, we occasionally see that the Rx or Tx sync signal drops to low. Don't we expect these sync signals to stay high stably? What are the reasons for the sync signal to drop to low?

    Thank you

    Tolga

  • 0 in reply to TOLGA KELES
    TI__Genius 17671 points

    Hi Tolga,

    The configuration that you are using is combining the Sync signals into a single signal for all ADCs and that Sync signal is routed to the H7 and H8, it is not lane specific. Similarly all DACs are sharing a single Sync signal and that signal is routed to N9 and P9.

    You are correct, the Sync signals should be stable once the JESD link is up. One reason that the Sync signal would go low is that the JESD link is not stable and the AFE or FPGA are attempting to re-establish the JESD link. Are you receiving any errors on the ADC or DAC JESD link?

    Regards,

    David Chaparro