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AFE7900 ADC ISSUE

Murat Bostanoglu
Prodigy 30 points
Other Parts Discussed in Thread: AFE7900

I have a custom board design with AFE7900 and Xilinx Xcku050 FPGA.  

I want to test my JESD lanes with registers B7h  (DAC JESD - TX_JESD_TEST_S IG_GEN_MODE ) and 108h, 109h (ADC JESD - RX1_JESD_TEST_SIG_GEN_MODE, RX2_JESD_TEST_SIG_GEN_MODE) by sending ramp signals. (I am sending this commands both AB and CD pages of AFE).

1) When I write the value 0x2 to the B7h register, I can see the Ramp signal from the FPGA, but when I disable the B7h register and apply an external signal to the AFE, I can only see the noise in the FPGA.

Will this test fully verify my JESD connection at TX side and what could be the cause of this Issue ?

2) When I write the value 0x2 to the 108h and 109h registers, I can verify with the spectrum analyzer that the Ramp signal comes out of the AFE, but there is no signal from all the AFEs on my board and I see the signal corrupted in some of them? (Also, I have checked this tests with my EVM and I know what is the output of AFE with same configurations)

Will this test fully verify my JESD connection at RX side and what could be the cause of this Issue ?

I need help on this problem?

Thanks in advance.

  • 0
    TI__Genius 14230 points

    Hi Murat,

    1) Seeing the ramp pattern on the FPGA side shows that AFE is setup correctly and that you have the correct lanes in use. How are you viewing the data to see that it is just noise? Can you confirm that your data unpacking is correct for the JESD format you are using? A couple of things to also look at are lane muxing and lane polarity. 

    2) This might be a similar issue to the ADC side. Can you check the data packing and confirm that the JESD parameters on the FPGA side match the AFE settings.

    Regards,

    David Chaparro