Other Parts Discussed in Thread: AFE7950, TSW14J57EVM,
I would like to evaluate AFE7950 using AFE7950EVM and TSW14J57EVM.
Now that I have finished setting up the device, I am proceeding with the work while referring to the user guide, but when I was proceeding with the automatic configuration in section 4.9 of the user guide, some errors occurred when I pressed the F5 key to execute.
I will attach the log, so could you tell me how to deal with it?
As for the LEDs, AFE7950 has D3 lighting, TSW14J57 has D1.3.8 lighting, D5.6.9 weak lighting, and D2.4.7 lighting off.
What does each default frequency described in Section 4.11 represent? NCO frequency = sampling rate, right? For example, if I want to input and evaluate a 3GHz signal, should I set it to 3000 with the command described in 4.12?
Thank you for your reply.
Workspace is cleared AFE79xxLibraryPG1p0 spi - USB Instrument created. resetDevice Purge MPSSE mode set Kintex RegProgrammer - USB Instrument created. Kintex RegProgrammer - USB Instrument created. Kintex RegProgrammer - USB Instrument created. #================ ERRORS:0, WARNINGS:0 ================# Power Card - USB Instrument created. Reset the FPGA and try again. Loaded Libraries #================ ERRORS:1, WARNINGS:0 ================# Selecting DAC Device : AFE79xx_2x2TX_14810 Error Status = 7002 Using HSDC Ready function to check if the GUI is Ready... Setting DAC Data Rate = 737280000.0 Setting DAC Option = 0 Setting DAC Preamble = 0 Generating Data from DAC Tone Generation.. Sending Data to DAC.. Error Status = 7002 Selecting DAC Device : AFE79xx_2x2TX_14810_B Error Status = 7002 The External Sysref Frequency should be an integer factor of: 3.84MHz 2T2R1F Number: 0 Valid Configuration: True laneRateRx: 14745.6 laneRateFb: 14745.6 laneRateTx: 14745.6 2T2R1F Number: 1 Valid Configuration: True laneRateRx: 14745.6 laneRateFb: 14745.6 laneRateTx: 14745.6 Device Initialization for ChipVersion: 1.3 LMK Clock Divider - Device registers reset. LMK Clock Divider - Device registers reset. REFCLOCK is used from LMK source, ensure board connections are ok to do the same DONOT_OPEN_Atharv_FULL - Device registers reset. chipType: 0xa chipId: 0x78 chipVersion: 0x11 SPIA has got control of PLL pages PLL Pages SPI control relinquished. Fuse farm load autoload done successful No autload error Fuse farm load autoload done successful No autload error //Firmware Version = 11000 //PG Version = 1 //Release Date [dd/mm/yy] = 10/7/19 patchSize=11697 //Patch Version = 165 //PG Version = 0 //Release Date [dd/mm/yy] = 27/11/21 SPIA has got control of PLL pages PLL Locked PLL Pages SPI control relinquished. SPIA has got control of PLL pages PLL Pages SPI control relinquished. SPIA has got control of PLL pages PLL Pages SPI control relinquished. SPIA has got control of PLL pages PLL Pages SPI control relinquished. Sysref Read as expected ###########Device DAC JESD-RX 0 Link Status########### lane0 Errors=0b10000111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; multiframe alignment error; lane1 Errors=0b10000111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; multiframe alignment error; lane2 Errors=0b10000111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; multiframe alignment error; lane3 Errors=0b10000111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; multiframe alignment error; CS State TX0: 0b10101010 . It is expected to be 0b10101010 FS State TX0: 0b00000000 . It is expected to be 0b01010101 Couldn't get the link up for device RX: 0; Alarms: 0x8787878700000000L ################################### ###########Device DAC JESD-RX 1 Link Status########### lane0 Errors=0b10000111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; multiframe alignment error; lane1 Errors=0b10000111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; multiframe alignment error; lane2 Errors=0b10000111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; multiframe alignment error; lane3 Errors=0b10000111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; multiframe alignment error; CS State TX0: 0b10101010 . It is expected to be 0b10101010 FS State TX0: 0b00000000 . It is expected to be 0b01010101 Couldn't get the link up for device RX: 1; Alarms: 0x8787878700000000L ################################### #================ ERRORS:13, WARNINGS:1 ================# Selecting ADC Device : AFE79xx_2x2RX_22210 Error Status = 7002 Using HSDC Ready function to check if the GUI is Ready... Passing ADC Output Data Rate = 368640000.0 Set Number of Samples per Channel = 16384 Starting normal capture.. Error Status = 7002 Selecting ADC Device : AFE79xx_2x2RX_22210_B Error Status = 7002 #Done executing .. AFE79xx/Automation/AFE79xx_TSW14J57_Mode7.py #End Time 2023-01-18 14:40:37.716000 #Execution Time = 129.820000172 s #================ ERRORS:3, WARNINGS:0 ================#
Hi David,