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AFE7950EVM: configuration

SM
Expert 1730 points
Part Number: AFE7950EVM
Other Parts Discussed in Thread: AFE7900, AFE7950, AFE7900EVM,

Hello,

    We are using the eval boards of both AFE7900 and AFE7950 (EVMs) connected to a ZCU102. 

Background: We have a design that works on the AFE7900EVM (specifically channels C and D are used). The register values were extracted from Latte's log (for AFE7900) and written to the AFE (again, working setup)

Now we would like to test the same working design on the AFE7950EVM. We replaced the 7900EVM with the 7950EVM. However we are unable to see any output from the Tx ports. The Rx ports are working (as captured through ILA). A digital loopback (Rx connected to Tx inside the FPGA) also doesn't give out any signal.(the signals can be seen on ILA). It seems that there is some setting in the AFE7950 which has to be configured differently.

We confirm that the AFE7950EVM is a working board (as we tested with a basic design and configured it directly from Latte).

qpll lock and rxlmfc_buffer_delay give the right values (on 7950EVM)

Thank you for your help in advance,

  • 0
    TI__Genius 11940 points

    Hi Shashank,

    When you are moving on to the AFE7950EVM are you updating the configuration file that you are using? The register writes that are needed to program the AFE7950 will be different so you would need to use Latte to generate an updated configuration file for the AFE7950.

    Regards,

    David Chaparro

  • 0 in reply to David Chaparro
    Expert 1730 points

    Hello David,

             We are seeing a difference in the log files generated between two versions of Latte. I am sending you the old and new (generated from previous and newer versions) log files by email. 

    The newer log is much bigger (20K lines compared to the previous log which is 8K lines). We compared the individual sections and following is the observation

    OLD NEW
    Enabling Efuse Clock  has 298 lines has 12682 lines
    Loading PLL Efuse trims has 295 lines has 350 lines
    Resetting Serders has 19 lines has 15 lines
    Configuring the SERDES  has 34 lines has 834 lines
    Configuring RRF Mode to TOP MCU  has 171 lines has 175 lines
    Configuring TX chain Parameters to TOP MCU has 301 lines has 844 lines
    Configuring Digital chain has 65 lines has 236 lines
    DAC Analog writes has 64 lines has 85 lines
    Requesting/releasing SPI Access to PLL pages  has 351 lines has 322 lines
    Configuring the JESD-DUC Data Muxes  has 26 lines has 34 lines
    Configuring DAC JESD RX  has 118 lines has 108 lines
    Checking Sysref Flags has 32 lines has 42 lines
    Removing TDD Pin Overrides  has 126 lines has 135 lines
    Removing TDD Pin Overrides  has 485 lines has 435 lines

    The enabling efuse clock sections is 12K lines more. Please advise. 

    Also for the same .py file used in latte, 

    in the comments at the beginning of the log: 

    old: 

    enableADCaveragingmode = [False,False] while in the new it is not present at all

    and 

    in the old

    enableDACinterleavermode = False while in the new it is True.

    Please advise and thank you for your help,

  • 0 in reply to SM
    Expert 1730 points

    Hello 

            Looking forward to your inputs.

    Thank you

  • 0 in reply to SM
    TI__Genius 11940 points

    Hi Shashank,

    The differences in the size of configuration files that you are seeing is expected and there should be no issues using this for the AFE7950. 

    Just to confirm are you using the latest version of Latte available in the secure folder? Although the enableADCavergingmode is not shown in the second configuration file there will be no issue as this is set to False by default. 

    The enableDacInterleavedMode parameter can be set in your script using the below command.

    sysParams.enableDacInterleavedMode=False. 

    Regards,

    David Chaparro 

  • 0 in reply to David Chaparro
    Expert 1730 points

    Hello David,

              May I ask you to please elaborate on these differences especially the first section (efuse which has a difference of 12K lines). We tried working with the new log file and it doesn't work. 

    Please tell us a way to disable the extra lines (if the previous smaller log works then why this difference). 

    2) Please also provide a working code set to use the C-api. 

    3) Please also provide the reference design for configuring the AFE from Xilinx FPGA (SPI programming from Xilinx FPGA)

    4) Please also provide the calculations for Tx and Rx NCOs and the way to program them over SPI.

    Regards,

  • 0 in reply to SM
    TI__Genius 11940 points

    Hi Shashank,

    1) The AFE7950 was designed first and the AFE7900 was designed afterwards with changes made to it. Some of the settings from the AFE7950 were added to the AFE7900 as defaults therefore reducing the number of writes required to program. What exact issue are you having with the log file for the AFE7950? Is there an error that you can share?

    2) In the AFE79xx secure folder you can find the CAFE files and example.

    3) I am working with my team to find how to share this with you.

    4) I will share this answer with you through email.

    Regards,

    David Chaparro

  • 0 in reply to David Chaparro
    Expert 1730 points

    Hello David,

        1) The issue that we are facing is that the qpll lock and rx_buffer values are changing as expected (after programming) but there is no signal coming out

    2) ok

    3) Looking forward to your input for this,

    4) There is  a discrepancy in the calculation you sent and the one generated by log. The calculation you sent seems logical though. 

    5)  For the same frequency setting, Eg: 4,200MHz in TxNCO, channel A and channel C log has different values: 

    One has: 0x16400000

    and the other has 0x16400002

    For 4,200 value: as per your formula the value is 0x5B255555 while latte produces: 0x16400000

    Please advise,

  • 0 in reply to SM
    Expert 1730 points

    Hello David,

             Looking forward to your reply.

  • 0 in reply to SM
    TI__Genius 11940 points

    Hi Shashank,

    Is this for the Rx or Tx? One thing to check is that you ran the AFE.TOP.overrideTdd(15,0,15) command. If on the Rx are you seeing anything or only zeros?

    Can you confirm that you have the following parameter set to 'True' in your script? If this is not set to 'True' then the AFE will optimize the FCW so it may not be equal to the value that was calculated. 

    AFE.systemStatus.txChainDirectCtrl = True

    Regards,

    David Chaparro 

  • 0 in reply to David Chaparro
    Expert 1730 points

    Hello David,

            1) May I ask what could be going wrong with the AFE7950? The qpll locks and the rx_buffer sets correctly but there is no output signal. 

    2) Please also provide the reference design for configuring the AFE from Xilinx FPGA (SPI programming from Xilinx FPGA)

    3) AFE.TOP.overrideTdd(15,0,15) is being run.

    AFE.systemStatus.txChainDirectCtrl = True is not set. 

    I am not clear about the calculations as how can the values be so different. 

    Regards,

  • 0 in reply to SM
    TI__Genius 11940 points

    Hi Shashank,

    1)  Are you receiving any DAC JESD errors when using the configuration file that you generated? 

    2) Our team is working on releasing this to the public. I will check on the exact timeline for this. 

    In regards to the AFE.systemStatus.txChainDirectCtrl parameter, if this parameter is not set to 'True' then in the background Latte and the update NCO macro are optimizing the FCW. If you want to directly set the NCO FCW using the calculated value you should set this to 'True'. Once this parameter has been set then the value in read back will match the value you calculate. 

    Regards,

    David Chaparro

  • 0 in reply to David Chaparro
    Expert 1730 points

    Hello David,

              1) We are programming the registers as per the log but not reading back anything. Is there any specific register that we should read to know about JESD errors? Also, rxlmfc_buffer_delay  register shows the right value which in our understanding was a reasonable indicator of everything written correctly (but now it may not be the case). 

    2) ok will wait for it

    3) We will add AFE.systemStatus.txChainDirectCtrl = True and try. However how do set the NCO values individually for each channel in rx and tx modes. 

    Thanks,

  • 0 in reply to SM
    Expert 1730 points

    Hello David,

             We added the txChainDirectCtrl line and got the following messages (without this directctrl line the script runs fine and everything works). (The scripts we are using are already sent to you by email).

    #================ ERRORS:0, WARNINGS:0 ================#

    #======

    #Executing .. AFE79xx/bringup/TI_IP_10Gbps_8Lane_ConfigLmk1_AFE7900.py

    #Start Time 2023-02-28 15:01:41.562000

    TX Infinite NCO not supported for 1KHz Raster Mode.

    In second Nyquist operation of TX NCO, DAC Interleaved mode is not supported.

    The External Sysref Frequency should be an integer factor of: 3.84MHz

    2T2R1F Number: 0

    Valid Configuration: False

    laneRateRx: 9830.4

    laneRateFb: 9830.4

    laneRateTx: 9830.4

    2T2R1F Number: 1

    Valid Configuration: False

    laneRateRx: 9830.4

    laneRateFb: 9830.4

    laneRateTx: 9830.4

    #Error: log() got an unexpected keyword argument 'title'

    # "AFE79xx/bringup/TI_IP_10Gbps_8Lane_ConfigLmk1_AFE7900.py", line 174, in

    # File "C:\Texas Instruments\Latte\lib\\AFE79xxLibraries\\AFE79xxLibraryPG1p0\resourceFiles\mFuncDecorator.py", line 88, in inDecorator

    # a=func(*args,**kwargs)

    # File "C:\Documents\Texas Instruments\Latte\lib\\AFE79xxLibraries\\AFE79xxLibraryPG1p0\mAfeLibrary.py", line 216, in deviceBringup

    # log(title='Invalid Configuration.',msg='Invalid Configuration. Please select Valid configuration. Refer to Log for Errors.')

    # TypeError: log() got an unexpected keyword argument 'title'

    #

    #

    #Done executing .. AFE79xx/bringup/TI_IP_10Gbps_8Lane_ConfigLmk1_AFE7900.py

    #End Time 2023-02-28 15:01:41.617000

    #Execution Time = 0.0550000667572 s

    #================ ERRORS:5, WARNINGS:0 ================#

  • 0 in reply to SM
    TI__Genius 11940 points

    Hi Shashank,

    1) The rx_lmfc_buffer_delay is only for the Rx and does not have any connections to the AFE's DACs. To check the DAC JESD for errors you can read back registers 0x118 - 0x11F in the DAC JESD page. More information on this can be found in the Register Set document, SBAU337. 

    3) In our previous email chain we described how to update the NCO values using the register writes for TxA. To update the other Tx channels you can change the page that you are writing to, using register the global register 0x19, as each Tx will have a page in TX TOP. The Rx will also be similar. 

    Regards,

    David Chaparro

  • 0 in reply to David Chaparro
    Expert 1730 points

    Hello David,

              3) The approach you advised was to first set the AFE.systemStatus.txChainDirectCtrl = True

    When we run the script with the above line we get the errors mentioned in my previous post. Please advise on what is going wrong. 

    Thanks,

  • 0 in reply to SM
    TI__Genius 11940 points

    Hi Shashank,

    Can you confirm that you are using the latest version of the GUI? I have tested this using the latest version that is available on the AFE79xx secure folder. Please try to update to the latest version and see if this fixes your error.

    Also, we can continue the discussion over email as we have the email chain going on.

    Regards,

    David Chaparro