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AFE7906: AFE7906

Rajashekar Etankar
Prodigy 120 points

Part Number: AFE7906

can u provide SERDES output group length matching tolerance among X8 STX lanes from ADC to Digital IC

  • 0
    TI__Mastermind 45670 points

    Hi Rajashekar,

    No length matching is required for a JESD interface in general.

    The internal FPGA elastic timing buffers take care of all the timing mismatch between the different lanes.

    If you need a boundary, I would use 250milli-inches/0.6cm or less.

    Regards,

    Rob