DAC JESD-Rx link errors

HI Zeljko,

The errors show that JESD receiver in AFE (DAC SERDES) did not align with Comma characters from FPGA SERDES transmit. 

As JESD clocks to the FPGA are output from LMK, that has to be programmed first and FPGA SERDES transmitter should be configured first before AFE can be configured for the link to come up. 

I see in your script that AFE.deviceBringup() is ran first and then LMK outputs were set. So as FPGA SERDES transmit is not configured by the time AFE.deviceBringup() is run, this error will happen. 

There are a few TI JESD204 IP reference designs with Xilinx dev kits in AFE79xx secure folder. Please follow the sequence shown in theses reference designs.  

AFE79xx secure folder can accessed at www.ti.com/myseurcesoftware. If you don't have access, submit request at https://www.ti.com/licreg/docs/swlicexportcontrol.tsp?form_id=318147&prod_no=AFE79XX-HSC-DESIGN&ref_url=ASC_DCC_DC-HSC

Regards,

Vijay

Hi Vijay,

Many thanks for the reply. In the reference design documents I managed to find a Word file where an outline of steps is presented:

In step 2 in the corresponding latte script the functions AFE.initializeConfig() and AFE.LMK.lmkConfig() are called, which seems to be along with what you said, that LMK needs to be set up first, followed by the FPGA configuration (step 3).

Then step 4 contains calls to AFE.deviceBringup() and AFE.TOP.overrideTdd(), which then, I guess, initiates the data exchange between the FPGA and the AFE?

Am I correct in this interpretation?

In addition, in my original code I do not have explicit calls to AFE.initializeConfig() and AFE.LMK.lmkConfig(). If I were to modify my script (from what is shown in my first post), do I need both of these functions, or only  AFE.LMK.lmkConfig()? I understand that they (and all the LMK settings contained in the original code) need to be specified before calls to AFE.deviceBringup() and AFE.TOP.overrideTdd().

I also see in the example scripts that before calling AFE.initializeConfig() and AFE.LMK.lmkConfig() functions setupParams.skipLmk is set to false then later in TI_IP_ConfigAfe.py script this value is changed to true before calling AFE.deviceBringup() and AFE.TOP.overrideTdd(). Is there a particular reason for this change in value?

Kind regards,

Željko

Hi Vijay,

A small update from my side:
Based on your reply, I looked into reference designs and there was a document entitled

TI204c Capture Setup for AFE79xx

which I used to get an idea on how to rearrange my current Latte script.

From there I understood that as a first step my lmk.head.page (LMK bypass controls) properties definition were to be migrated before calls to deviceBringup() function. Initially I also included AFE.LMK.lmkConfig() function to the call, just after the bypass controls, but I've learned that calling AFE.LMK.lmkConfig() resets the LMK controls. It is for this reason I left it out from my script.

In the second step FPGA is programmed and I can see it achieves qpll lock from the AFE side.

However, in the last step where I try to run AFE.deviceBringup() I still see the same error as before:

Also, from the FPGA side no qpll lock can be seen anymore after this.

It seems from this as if AFE.deviceBringup() additionally modifies the LMK settings from my bypass settings, or perhaps resets it. Can you perhaps provide some insights on this?

Please find also enclosed my modified scripts:

##########                  Board bringup procedure                  ##########

#mainWindow.clearSession()
#base_directory = "C:\\Users\\a0217443\\Documents\\Texas Instruments\\Latte\\projects\\AFE79xx\\bringup\\"
#mainWindow.runFile(base_directory + r"setup.py")
#mainWindow.runFile(base_directory + r"devInit.py")

##########                     General settings:                     ##########

# VLBI Tx frequency plan details:
custom_clk 							= 3

ncoFreqModes 						= ["1KHz", "FCW"]
Fnco_tx1 							= 2245.0
Fnco_rx1							= 500.0

if (custom_clk == 1):
	f0 								= 163.68
	Nrx								= 18
	Nddc							= 6
	Ntx 							= 4
	NFRef							= 1
	NfpgaRefClk						= 1
	NinputClk						= 1
	LMFSHdRx              			= ['22210', '22210', '22210', '22210']#['44210', '44210', '44210', '44210']#
	LMFSHdFb						= ['22210', '22210']
	LMFSHdTx						= ['22210', '22210', '22210', '22210']#['44210', '44210', '44210', '44210']#
	syncLoopBack 					= False
	jesdLoopbackEn					= True
elif custom_clk == 0:
	f0 								= 122.88
	Nrx								= 24
	Nddc							= 12
	Ntx 							= 3
	NFRef							= 4
	NfpgaRefClk						= 2
	NinputClk						= 12
	LMFSHdRx              			= ['24410', '24410', '24410', '24410']
	LMFSHdFb						= ['24410', '24410']
	LMFSHdTx						= ['24410', '24410', '24410', '24410']
	syncLoopBack					= False
	jesdLoopbackEn					= True
elif custom_clk == 2:
	f0 								= 163.68
	Nrx								= 12
	Nddc							= 6
	Ntx 							= 3#6
	NFRef							= 1
	NfpgaRefClk						= 1
	NinputClk						= 1
	LMFSHdRx              			= ['22210', '22210', '22210', '22210']#['44210', '44210', '44210', '44210']
	LMFSHdFb						= ['22210', '22210']
	LMFSHdTx						= ['22210', '22210', '22210', '22210']#['44210', '44210', '44210', '44210']
	syncLoopBack 					= False
	jesdLoopbackEn					= True
elif custom_clk == 3:
	f0 								= 163.68
	Nrx								= 12
	Nddc							= 6
	Ntx 							= 3#6
	NFRef							= 1
	NfpgaRefClk						= 1
	NinputClk						= 1
	LMFSHdRx              			= ['44210', '44210', '44210', '44210']
	LMFSHdFb						= ['42210', '42210']
	LMFSHdTx						= ['44210', '44210', '44210', '44210']
	syncLoopBack 					= True
	jesdLoopbackEn					= False
	
Nduc								= Nddc*Ntx

# AFE general settings
AFE.systemStatus.loadTrims			= 1
setupParams.skipFpga 				= 1
setupParams.fpgaRefClk 				= f0*NfpgaRefClk
sysParams							= AFE.systemParams
sysParams.FRef 						= f0*NFRef

##########               Analog settings: AFE 79XX EVM               ##########

# General system settings	
sysParams.RRFMode   				= 0
sysParams.modeTdd					= 0
sysParams.adcSelect0				= [0, 1, 2]
sysParams.adcSelect1				= [0, 1, 2]
sysParams.useSpiSysref				= 0
sysParams.sysrefTermination			= 0
sysParams.ncoFreqMode				= ncoFreqModes[custom_clk != 0]
sysParams.spiMode					= 1

# ADC settings
sysParams.FadcRx 					= f0*Nrx
sysParams.rxEnable 					= [1, 1, 1, 1]
sysParams.externalClockRx 			= 0
sysParams.halfRateModeRx 			= [0, 0]
sysParams.ddcFactorRx 				= [Nddc, Nddc, Nddc, Nddc]
sysParams.numBandsRx 				= [0, 0, 0, 0]
sysParams.numRxNCO 					= 1
sysParams.ncoRxMode					= [0, 0]
sysParams.broadcastRxNcoSel			= 0
sysParams.rxNco0 					= [ [Fnco_rx1, Fnco_rx1], 
										[870.0, 870.0], 
										[637.5, 637.5], 
										[637.5, 637.5]]
sysParams.rxNco1 					= [ [Fnco_rx1, Fnco_rx1], 
										[870.0, 870.0], 
										[637.5, 637.5], 
										[637.5, 637.5]]

# FB settings
sysParams.FadcFb					= sysParams.FadcRx
sysParams.fbEnable 					= [0, 0]
sysParams.halfRateModeFb 			= [0, 0]
sysParams.ddcFactorFb 				= [Nddc, Nddc]
sysParams.numBandsFb				= [0, 0]
sysParams.numFbNCO 					= 1
sysParams.ncoFbMode					= 0
sysParams.fbNco0 					= [1000, 1000]
sysParams.fbNco1 					= [1000, 1000]
sysParams.fbNco2 					= [1000, 1000]
sysParams.fbNco3 					= [1000, 1000]

# DAC settings
# DAC sampling rate must fall into one of the following frequency ranges (due to pll restrictions): [7.2 GHz, 7.68 GHz] or [8.8 GHz, 9.1 GHz] or [9.7 GHz, 10.24 GHz] or [11.6 GHz, 12.08 GHz]
sysParams.Fdac 						= sysParams.FadcRx*Ntx
sysParams.txEnable 					= [1, 1, 1, 1]
sysParams.externalClockTx			= 0
sysParams.halfRateModeTx 			= [0, 0]
sysParams.ducFactorTx 				= [Nduc, Nduc, Nduc, Nduc]
sysParams.numBandsTx 				= [0, 0, 0, 0]
sysParams.numTxNCO 					= 1
sysParams.combineDucMode 			= [0, 0]
sysParams.enableDacInterleavedMode 	= 0
sysParams.ncoTxMode					= [0, 0]
sysParams.broadcastTxNcoSel			= 0
sysParams.txNco0	 				= [ [Fnco_tx1, Fnco_tx1],
										[5020.0, 5020.0], 
										[8212.5, 8212.5], 
										[6812.5, 6812.5]]
sysParams.txNco1 					= [ [Fnco_tx1, Fnco_tx1],
										[5020.0, 5020.0], 
										[8212.5, 8212.5], 
										[6812.5, 6812.5]]
										
##########              Clock distribution mode setting              ##########

setupParams.skipLmk					= 0
lmkParams.pllEn 					= (custom_clk == 0)
lmkParams.inputClk 					= f0*NinputClk
lmkParams.sysrefFreq				= lmkParams.inputClk#f0*Nrx/1024
lmkParams.lmkFrefClk				= 1
lmkParams.lmkPulseSysrefMode 		= 0
#AFE.systemStatus.sysrefFreq		= lmkParams.inputClk
#AFE.LMK.lmkConfig()

##########               JESD204 settings AFE 79XX EVM               ##########

sysParams.topLevelSystemMode		= 'StaticTDDMode'
sysParams.jesdSystemMode			= [3, 3]
sysParams.serdesFirmware			= 1
sysParams.jesdABLvdsSync			= 1
sysParams.jesdCDLvdsSync			= 1
sysParams.syncLoopBack				= syncLoopBack
sysParams.jesdLoopbackEn			= jesdLoopbackEn
sysParams.setIlaParams				= 1
sysParams.jesdTxIlaM				= [8, 8, 2, 8, 8, 2]
sysParams.jesdTxIlaLid				= [0, 1, 2, 3, 4, 5, 6, 7]
sysParams.jesdTxIlaL				= [4, 4, 2, 4, 4, 2]
	
	
sysParams.LMFSHdRx					= LMFSHdRx
sysParams.jesdRxProtocol			= [0, 0]
sysParams.jesdRxLaneMux				= [0, 1, 2, 3, 4, 5, 6, 7]
sysParams.jesdRxRbd					= [4, 4]
sysParams.rxJesdTxScr				= [1, 1, 1, 1]
sysParams.rxJesdTxK					= [16, 16, 16, 16]
sysParams.rxJesdTxSyncMux			= [0, 0, 0, 0]
sysParams.rxDataMux					= [0, 1, 2, 3, 4, 5, 6, 7]
sysParams.serdesRxLanePolarity		= [0, 0, 0, 0, 0, 0, 0, 0]
sysParams.adcDataMuxEn				= 0
	
	
sysParams.LMFSHdFb					= LMFSHdFb
sysParams.fbJesdTxScr				= [1, 1]
sysParams.fbJesdTxK					= [16, 16]
sysParams.fbJesdTxSyncMux			= [0, 0]
sysParams.fbDataMux					= [0, 1]
	
sysParams.LMFSHdTx					= LMFSHdTx
sysParams.jesdTxProtocol			= [0, 0]
sysParams.jesdTxLaneMux				= [0, 1, 2, 3, 4, 5, 6, 7]
#sysParams.jesdTxRbd					= [4, 4]
sysParams.jesdRxScr					= [1, 1, 1, 1]
sysParams.jesdRxK					= [16, 16, 16, 16]
sysParams.jesdRxSyncMux				= [0, 0, 0, 0]
sysParams.txDataMux					= [0, 1, 2, 3, 4, 5, 6, 7]
sysParams.serdesTxLanePolarity		= [0, 0, 0, 0, 0, 0, 0, 0]
#sysParams.dacDataMuxEn				= 0
#sysParams.serdesTxPreCursor			= [6, 6, 6, 6, 6, 6, 6, 6]
#sysParams.serdesTxPostCursor		= [0, 0, 0, 0, 0, 0, 0, 0]
#sysParams.serdesTxMainCursor		= [3, 0, 0, 0, 0, 0, 0, 3]


##########                         Dummy txt                         ##########

sysParams.gpioMapping={ 'H8': 'ADC_SYNC0',
						'H7': 'ADC_SYNC1',
						'N8': 'ADC_SYNC2',
						'N7': 'ADC_SYNC3',
						'H9': 'DAC_SYNC0',
						'G9': 'DAC_SYNC1',
						'N9': 'DAC_SYNC2',
						'P9': 'DAC_SYNC3',
						'P14': 'GLOBAL_PDN',
						'K14': 'FBABTDD',
						'R6': 'FBCDTDD',
						'H15': ['TXATDD','TXBTDD'],
						'V5': ['TXCTDD','TXDTDD'],
						'E7': ['RXATDD','RXBTDD'],
						'R15': ['RXCTDD','RXDTDD']}

lmk.rawWriteLogEn 					= 1
lmk.logEn 							= 1

logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat				= 0x01
logDumpInst.rewriteFile				= 1
logDumpInst.rewriteFileFormat4		= 1

device.optimizeWrites				= 0
device.rawWriteLogEn				= 1
device.delay_time                   = 0


AFE.initializeConfig()
# Force Latte to program the LMK outputs (relevant to the FPGA) in bypass/distribution mode
lmk.head.page.DCLK0_SDCLK1_controls.Analog_Dig_Delay.dclk_mux_lt_1_0_gt_=2
lmk.head.page.DCLK8_SDCLK9_controls.Analog_Dig_Delay.dclk_mux_lt_1_0_gt_=2
lmk.head.page.DCLK12_SDCLK13_controls.Analog_Dig_Delay.dclk_mux_lt_1_0_gt_=2
#AFE.LMK.lmkConfig()

AFE.saveCAfeParamsFile()

# C273 (GTXCLK_P, yellow) is now at 163.68 MHz (sine-wave-looking signal, with noticed background noise, however, enough for FPGA to get a PLL lock)
# C259 (FPGA_CLK2P/FPGA_REFCLK2_P, red) is now at 163.68 MHz (sine-wave-looking signal, with noticed background noise, however, enough for FPGA to get a PLL lock)
# R353 (CAR_SYSREF_P/FPGA_SYSREF_P, green) is now at ?? MHz (Hard to really tell)

AFE.deviceBringup()
AFE.TOP.overrideTdd(15,3,15)

Hi Vijayendra Varma Siddamsetty,

I just wanted to check if there is any update on this.

Kind regards,

Zeljko