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AFE7920EVM: AFE7920EVM: Rx JESD issues: Frame errors, SerDes FIFO errors, and lane errors

Zeljko Jelic
Intellectual 318 points
Part Number: AFE7920EVM
Other Parts Discussed in Thread: AFE7950EVM

Hi Team,

In the setup I have (sinewave signal generator to ADC A of AFE7920EVM, Kintex 7 FPGA+AFE7920EVM at external clock reference 163.68 MHz, AFE7920EVM A and B DAC outputs connected to the spectrum analyzers), there have been some errors raised by AFE79xx software (latest iteration of Latte software).

The bringup procedure for the setup is staged in 6 steps (see scripts attached at bottom of this post) as follows:

  • step 0 - run mandatory AFE79xx scripts (setup.py and devInit.py)
  • step 1 - define system properties (external clock frequency, NCO frequency, etc.) and store in local variables
  • step 2 - apply RF AFE properties selected by user
  • step 3 - apply JESD AFE properties set by user
  • step 4 - apply LMK settings set by user
  • step 5 - initialize FPGA as described in reference design documents from AFE7920EVM TI secure folder (no dedicated script in Python for Latte, this is done manually in Vivado)
    1. here is also confirmed that pll clock in FPGA is present
    2. FPGA confirms that after reset there is high Rx sync signal
    3. FPGA confirms that after reset there is high Tx sync signal (value f corresponding to 4 syncs from AFE, all high value), but this value changes to a lower one (value c, corresponding to 2 high and 2 low syncs from AFE) after call to AFE.deviceBringup() in next step
    4. FPGA sends BOC signal via JESD to AFE DACs
  • step 6 - do the AFE bringup, followed by call to AFE.TOP.overrideTdd(15, 3, 15)

Step 6 is interrupted by errors (log shown below) after ~30-40s.

On the spectrum analyzers I see that DACs A and B are sending nonsense data after the error is raised (possibly due to JESD errors we get).

To be sure that there is some communication between AFE and FPGA, I repeat the procedure with steps 0-5, and instead of step 6, I send ramp signal from ADC to FPGA and also ramp to the DAC outputs.

By reading the contents of incoming ADC data in the FPGA we see ramp-like sample values (adjacent samples get incremented by the value specified in the AFE.JESD.ADCJESD[topNr].adcRampTestPattern(chnnlNo, TxRampEnable, rampStepSize-1)), which kind of confirms FPGA can get the ADC data (still no external sinewave, though). Also ADC ramps seem to be a bit missaligned in the FPGA however, but this is probably due to FPGA delay alignment (hopefully not an issue caused by Latte scripts).

On the other side, spectrum analyzer confirms ramp-like spectrum at DAC A and B outputs, which is also good. So it seems that AFE can send data and can propagate received data from JESD Rx to DACs, but due to the errors we see, it cannot received data from FPGA via JESD interface.

Could you please provide some insights into this and help us resolve the issue? It is quite critical for us to have this setup working.

The full AFE79xx software log transcript is as follows:

Workspace is cleared

AFE79xxLibraryPG1p0

spi - USB Instrument created.

resetDevice

Purge

Kintex RegProgrammer - USB Instrument created.

Kintex RegProgrammer - USB Instrument created.

Kintex RegProgrammer - USB Instrument created.

#================ ERRORS:0, WARNINGS:0 ================#

Power Card - USB Instrument created.

Reset the FPGA and try again.

Loaded Libraries

Refreshed GUI

#================ ERRORS:1, WARNINGS:0 ================#

************************************************************

Mandatory AFE initialization complete

************************************************************

#Done executing .. AFE79xx/bringup/AWS_step0_EVMsetup.py

#End Time 2023-03-16 12:23:08.208000

#Execution Time = 28.9049999714 s

#================ ERRORS:0, WARNINGS:0 ================#

#======

#Executing .. AFE79xx/bringup/AWS_step1_ParsDefine.py

#Start Time 2023-03-16 12:23:19.864000

Tx & Rx LMFSHd settings: 44210

------------------------------------------------------------

User configuration:

Digital repeater

DAC sampling in X band disabled

LVDS sync disabled - ADC and DAC sync enabled

External clock reference used: 163.68MHz

------------------------------------------------------------

************************************************************

User parametrization complete

************************************************************

#Done executing .. AFE79xx/bringup/AWS_step1_ParsDefine.py

#End Time 2023-03-16 12:23:19.873000

#Execution Time = 0.00899982452393 s

#================ ERRORS:0, WARNINGS:0 ================#

#======

#Executing .. AFE79xx/bringup/AWS_step2_AFEsetup.py

#Start Time 2023-03-16 12:23:37.507000

ADC sampling rate: 1964.16MHz

ADC down-conversion factors: [6, 6, 6, 6]

ADC NCOs: 500.0MHz, 870.0MHz, 637.5MHz, 637.5MHz

FB ADC sampling rate: 1964.16MHz

FB ADC down-conversion factors: [6, 6]

FB ADC NCOs: 1000MHz, 1000MHz

DAC sampling rate: 5892.48MHz

DAC up-conversion factors: [18, 18, 18, 18]

DAC NCOs: 2245.0MHz, 5020.0MHz, 8212.5MHz, 6812.5MHz

************************************************************

Analog front end setup complete

************************************************************

#Done executing .. AFE79xx/bringup/AWS_step2_AFEsetup.py

#End Time 2023-03-16 12:23:37.517000

#Execution Time = 0.00999999046326 s

#================ ERRORS:0, WARNINGS:0 ================#

#======

#Executing .. AFE79xx/bringup/AWS_step3_JESDsetup.py

#Start Time 2023-03-16 12:23:45.539000

************************************************************

JESD setup complete

************************************************************

#Done executing .. AFE79xx/bringup/AWS_step3_JESDsetup.py

#End Time 2023-03-16 12:23:45.555000

#Execution Time = 0.0160000324249 s

#================ ERRORS:0, WARNINGS:0 ================#

#======

#Executing .. AFE79xx/bringup/AWS_step4_LMKsetup.py

#Start Time 2023-03-16 12:23:48.729000

The External Sysref Frequency should be an integer factor of: 5.115MHz

2T2R1F Number: 0

Valid Configuration: True

laneRateRx: 6547.2

laneRateFb: 6547.2

laneRateTx: 6547.2

2T2R1F Number: 1

Valid Configuration: True

laneRateRx: 6547.2

laneRateFb: 6547.2

laneRateTx: 6547.2

LMK Clock Divider - Device registers reset.

LMK Clock Divider - Device registers reset.

************************************************************

LMK setup complete

************************************************************

#Done executing .. AFE79xx/bringup/AWS_step4_LMKsetup.py

#End Time 2023-03-16 12:23:49.844000

#Execution Time = 1.11500000954 s

#================ ERRORS:0, WARNINGS:0 ================#

#======

#Executing .. AFE79xx/bringup/AWS_step6_AFEbringup.py

#Start Time 2023-03-16 12:24:36.659000

The External Sysref Frequency should be an integer factor of: 5.115MHz

2T2R1F Number: 0

Valid Configuration: True

laneRateRx: 6547.2

laneRateFb: 6547.2

laneRateTx: 6547.2

2T2R1F Number: 1

Valid Configuration: True

laneRateRx: 6547.2

laneRateFb: 6547.2

laneRateTx: 6547.2

LMK and FPGA Configured.

DONOT_OPEN_Atharv_FULL - Device registers reset.

chipType: 0xa

chipId: 0x78

chipVersion: 0x11

AFE Reset Done

Fuse farm load autoload done successful

No autload error

Fuse farm load autoload done successful

No autload error

//Firmware Version = 11000

//PG Version = 1

//Release Date [dd/mm/yy] = 10/7/19

patchSize=11697

//Patch Version = 165

//PG Version = 0

//Release Date [dd/mm/yy] = 27/11/21

AFE MCU Wake up done and patch loaded.

PLL Locked

AFE PLL Configured.

AFE SerDes Configured.

AFE Digital Chains configured.

AFE TX Analog configured.

AFE RX Analog configured.

AFE FB Analog configured.

AFE JESD configured.

AFE AGC configured.

AFE GPIO configured.

Sysref Read as expected

###########Device DAC JESD-RX 0 Link Status###########

Serdes-FIFO error for lane 0: 1

Frame Sync error (unexpected k28.5) for lane 0: 1

Serdes-FIFO error for lane 1: 1

Frame Sync error (unexpected k28.5) for lane 1: 1

Serdes-FIFO error for lane 2: 1

Frame Sync error (unexpected k28.5) for lane 2: 1

Serdes-FIFO error for lane 3: 1

Frame Sync error (unexpected k28.5) for lane 3: 1

lane0 Errors=0b11001111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; frame alignment error; multiframe alignment error;

lane1 Errors=0b11001111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; frame alignment error; multiframe alignment error;

lane2 Errors=0b11001111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; frame alignment error; multiframe alignment error;

lane3 Errors=0b11001111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; frame alignment error; multiframe alignment error;

CS State TX0: 0b00000000 . It is expected to be 0b10101010

FS State TX0: 0b01010101 . It is expected to be 0b01010101

Couldn't get the link up for device RX: 0; Alarms: 0xcfcfcfcff000f000L

###################################

###########Device DAC JESD-RX 1 Link Status###########

lane0 Errors=0b1111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values;

lane1 Errors=0b0111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error;

lane2 Errors=0b0111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error;

lane3 Errors=0b0111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error;

CS State TX0: 0b10101010 . It is expected to be 0b10101010

FS State TX0: 0b01010101 . It is expected to be 0b01010101

Couldn't get the link up for device RX: 1; Alarms: 0x707070f00000000L

###################################

AFE Configuration Complete

************************************************************

AFE bringup complete

************************************************************

#Done executing .. AFE79xx/bringup/AWS_step6_AFEbringup.py

#End Time 2023-03-16 12:25:15.228000

#Execution Time = 38.5690000057 s

#================ ERRORS:18, WARNINGS:0 ================#

Kind regards,

Zeljko

step 0 script

##########               Board initialization procedure               ##########

mainWindow.clearSession()
base_directory = "C:\\Users\\laboadmin\\Documents\\Texas Instruments\\Afe79xxLatte\\projects\\AFE79xx\\bringup\\"
mainWindow.runFile(base_directory + r"setup.py")
mainWindow.runFile(base_directory + r"devInit.py")


info('')
info('************************************************************')
info('          Mandatory AFE initialization complete')
info('************************************************************')
info('')

step 1 script

##########                     General settings:                     ##########

# VLBI Tx frequency plan details:
custom_clk 							= 2											# Pick AFE scenario.
separate_runtime 					= 1											# Pick bringup staging scenario.
enableAnalogRepeater 				= False										# Enable/disable AFE in analog loopback configuration (DACs transmitting from ADCs).
XbandEnable							= False#True								# Enable/disable DAC sampling rate in X band.
dualLanePerSignal					= False#True								# Pick 2 lanes (True) or 4 lanes (False) to transmit signal via JESD lines.
enableAdcDacSync					= True										# Enable sync signal between ADCs and DACs and FPGA by disabling LVDS sync that fixes GPIO pins.


ncoFreqModes 						= ["1KHz", "FCW"]
Fnco_tx1 							= 2245.0
Fnco_rx1							= 500.0
syncLoopBack						= bool(1-enableAnalogRepeater)
jesdLoopbackEn 						= bool(enableAnalogRepeater)
enableLVDSsync						= bool(1-enableAdcDacSync)
fbJesdTxSyncMux						= 3 if enableLVDSsync else 1
if enableAnalogRepeater:
	separate_runtime = 0


if custom_clk == 0:
	# TI template configuration at different clock reference
	f0 								= 122.88
	Nrx								= 24
	Nddc							= 12
	Ntx 							= 3
	NFRef							= 4
	NfpgaRefClk						= 2
	NinputClk						= 12
	LMFSHdRx              			= ['24410', '24410', '24410', '24410']
	LMFSHdFb						= ['24410', '24410']
	LMFSHdTx						= ['24410', '24410', '24410', '24410']
	jesdSystemMode					= [3, 3]
elif (custom_clk == 1):
	# Desired configuration with proper data rates, sampling rates, and bandwidths
	f0 								= 163.68
	Nrx								= 18
	Nddc							= 6
	Ntx 							= 4
	NFRef							= 1
	NfpgaRefClk						= 1
	NinputClk						= 1
	LMFSHdRx              			= ['22210', '22210', '22210', '22210']
	LMFSHdFb						= ['22210', '22210']
	LMFSHdTx						= ['22210', '22210', '22210', '22210']
	jesdSystemMode					= [3, 3]
elif custom_clk == 2:
	# Symmetric JESD configuration
	f0 								= 163.68
	Nrx								= 12
	Nddc							= 6
	NFRef							= 1
	NfpgaRefClk						= 1
	NinputClk						= 1
	LMFSHdFb						= ['22210', '22210']
	Ntx 							= 5 if XbandEnable else 3
	Nlanes 							= '2' if dualLanePerSignal else '4'
	Nconv 							= Nlanes
	LMFSHdTx 						= [Nlanes+Nconv+'210']*4
	LMFSHdRx              			= LMFSHdTx
	jesdSystemMode					= [3, 3]
	
Nduc								= Nddc*Ntx
info('Tx & Rx LMFSHd settings: '+LMFSHdTx[0])


info('')
info('------------------------------------------------------------')
info('User configuration:')
if enableAnalogRepeater:
	info('     Analog repeater') 
else:
	info('     Digital repeater')
if XbandEnable:
	info('     DAC sampling in X band enabled') 
else:
	info('     DAC sampling in X band disabled')
if enableAdcDacSync:
	info('     LVDS sync disabled - ADC and DAC sync enabled') 
else:
	info('     LVDS sync enabled - ADC and DAC sync disabled')
if custom_clk:
	info('     External clock reference used: '+str(f0)+'MHz')
else:
	info('     Internal AFE clock reference used: '+str(f0)+'MHz')
info('------------------------------------------------------------')


info('')
info('************************************************************')
info('          User parametrization complete')
info('************************************************************')
info('')

step 2 script

# AFE general settings
AFE.systemStatus.loadTrims			= 1
setupParams.skipFpga 				= 1
setupParams.fpgaRefClk 				= f0*NfpgaRefClk
sysParams							= AFE.systemParams
sysParams.FRef 						= f0*NFRef

##########               Analog settings: AFE 79XX EVM               ##########

# General system settings	
sysParams.RRFMode   				= 0
sysParams.modeTdd					= 0
sysParams.adcSelect0				= [0, 1, 2]
sysParams.adcSelect1				= [0, 1, 2]
sysParams.useSpiSysref				= 0
sysParams.sysrefTermination			= 0
sysParams.ncoFreqMode				= ncoFreqModes[custom_clk != 0]
sysParams.spiMode					= 1

# ADC settings
sysParams.FadcRx 					= f0*Nrx
info('ADC sampling rate: '+str(sysParams.FadcRx)+'MHz')
sysParams.rxEnable 					= [1, 1, 1, 1]
sysParams.externalClockRx 			= 0
sysParams.halfRateModeRx 			= [0, 0]
sysParams.ddcFactorRx 				= [Nddc, Nddc, Nddc, Nddc]
info('ADC down-conversion factors: '+str(sysParams.ddcFactorRx))
sysParams.numBandsRx 				= [0, 0, 0, 0]
sysParams.numRxNCO 					= 1
sysParams.ncoRxMode					= [0, 0]
sysParams.broadcastRxNcoSel			= 0
sysParams.rxNco0 					= [ [Fnco_rx1, Fnco_rx1], 
										[870.0, 870.0], 
										[637.5, 637.5], 
										[637.5, 637.5]]
info('ADC NCOs: '+str(sysParams.rxNco0[0][0])+'MHz, '+str(sysParams.rxNco0[1][0])+'MHz, '+str(sysParams.rxNco0[2][0])+'MHz, '+str(sysParams.rxNco0[3][0])+'MHz')
sysParams.rxNco1 					= [ [Fnco_rx1, Fnco_rx1], 
										[870.0, 870.0], 
										[637.5, 637.5], 
										[637.5, 637.5]]

# FB settings
sysParams.FadcFb					= sysParams.FadcRx
info('FB ADC sampling rate: '+str(sysParams.FadcFb)+'MHz')
sysParams.fbEnable 					= [0, 0]
sysParams.halfRateModeFb 			= [0, 0]
sysParams.ddcFactorFb 				= [Nddc, Nddc]
info('FB ADC down-conversion factors: '+str(sysParams.ddcFactorFb))
sysParams.numBandsFb				= [0, 0]
sysParams.numFbNCO 					= 1
sysParams.ncoFbMode					= 0
sysParams.fbNco0 					= [1000, 1000]
sysParams.fbNco1 					= [1000, 1000]
sysParams.fbNco2 					= [1000, 1000]
sysParams.fbNco3 					= [1000, 1000]
info('FB ADC NCOs: '+str(sysParams.fbNco0[0])+'MHz, '+str(sysParams.fbNco1[0])+'MHz')

# DAC settings
# DAC sampling rate must fall into one of the following frequency ranges (due to pll restrictions): [7.2 GHz, 7.68 GHz] or [8.8 GHz, 9.1 GHz] or [9.7 GHz, 10.24 GHz] or [11.6 GHz, 12.08 GHz]
sysParams.Fdac 						= sysParams.FadcRx*Ntx
info('DAC sampling rate: '+str(sysParams.Fdac)+'MHz')
sysParams.txEnable 					= [1, 1, 1, 1]
sysParams.externalClockTx			= 0
sysParams.halfRateModeTx 			= [0, 0]
sysParams.ducFactorTx 				= [Nduc, Nduc, Nduc, Nduc]
info('DAC up-conversion factors: '+str(sysParams.ducFactorTx))
sysParams.numBandsTx 				= [0, 0, 0, 0]
sysParams.numTxNCO 					= 1
sysParams.combineDucMode 			= [0, 0]
sysParams.enableDacInterleavedMode 	= 0
sysParams.ncoTxMode					= [0, 0]
sysParams.broadcastTxNcoSel			= 0
sysParams.txNco0	 				= [ [Fnco_tx1, Fnco_tx1],
										[5020.0, 5020.0], 
										[8212.5, 8212.5], 
										[6812.5, 6812.5]]
sysParams.txNco1 					= [ [Fnco_tx1, Fnco_tx1],
										[5020.0, 5020.0], 
										[8212.5, 8212.5], 
										[6812.5, 6812.5]]
info('DAC NCOs: '+str(sysParams.txNco0[0][0])+'MHz, '+str(sysParams.txNco0[1][0])+'MHz, '+str(sysParams.txNco0[2][0])+'MHz, '+str(sysParams.txNco0[3][0])+'MHz')


info('')
info('************************************************************')
info('          Analog front end setup complete')
info('************************************************************')
info('')

step 3 script

##########               JESD204 settings AFE 79XX EVM               ##########

sysParams.topLevelSystemMode		= 'StaticTDDMode'
sysParams.jesdSystemMode			= jesdSystemMode
sysParams.serdesFirmware			= 1
sysParams.jesdABLvdsSync			= enableLVDSsync
sysParams.jesdCDLvdsSync			= enableLVDSsync
sysParams.syncLoopBack				= syncLoopBack
sysParams.jesdLoopbackEn			= jesdLoopbackEn
	
	
sysParams.LMFSHdRx					= LMFSHdRx
sysParams.jesdRxProtocol			= [0, 0]
sysParams.jesdRxLaneMux				= [0, 1, 2, 3, 4, 5, 6, 7]
sysParams.jesdRxRbd					= [4, 4]
sysParams.rxJesdTxScr				= [1, 1, 1, 1]
sysParams.rxJesdTxK					= [16, 16, 16, 16]
sysParams.rxJesdTxSyncMux			= [0, 0, 0, 0]
sysParams.rxDataMux					= [0, 1, 2, 3, 4, 5, 6, 7]
sysParams.serdesRxLanePolarity		= [0, 0, 0, 0, 0, 0, 0, 0]
sysParams.adcDataMuxEn				= 0
	
	
sysParams.LMFSHdFb					= LMFSHdFb
sysParams.fbJesdTxScr				= [1, 1]
sysParams.fbJesdTxK					= [16, 16]
sysParams.fbJesdTxSyncMux			= [fbJesdTxSyncMux, fbJesdTxSyncMux]
sysParams.fbDataMux					= [0, 1]
	
	
sysParams.LMFSHdTx					= LMFSHdTx
sysParams.jesdTxProtocol			= [0, 0]
sysParams.jesdTxLaneMux				= [0, 1, 2, 3, 4, 5, 6, 7]
#sysParams.jesdTxRbd					= [4, 4]
sysParams.jesdRxScr					= [1, 1, 1, 1]
sysParams.jesdRxK					= [16, 16, 16, 16]
sysParams.jesdRxSyncMux				= [0, 0, 0, 0]
sysParams.txDataMux					= [0, 1, 2, 3, 4, 5, 6, 7]
sysParams.serdesTxLanePolarity		= [0, 0, 0, 0, 0, 0, 0, 0]
#sysParams.dacDataMuxEn				= 0
#sysParams.serdesTxPreCursor			= [6, 6, 6, 6, 6, 6, 6, 6]
#sysParams.serdesTxPostCursor		= [0, 0, 0, 0, 0, 0, 0, 0]
#sysParams.serdesTxMainCursor		= [3, 0, 0, 0, 0, 0, 0, 3]
sysParams.setIlaParams				= 1
sysParams.jesdTxIlaM				= [8, 8, 2, 8, 8, 2]
sysParams.jesdTxIlaLid				= [0, 1, 2, 3, 4, 5, 6, 7]
sysParams.jesdTxIlaL				= [4, 4, 2, 4, 4, 2]


##########                         Dummy txt                         ##########

sysParams.gpioMapping={ 'H8': 'ADC_SYNC0',
						'H7': 'ADC_SYNC1',
						'N8': 'ADC_SYNC2',
						'N7': 'ADC_SYNC3',
						'H9': 'DAC_SYNC0',
						'G9': 'DAC_SYNC1',
						'N9': 'DAC_SYNC2',
						'P9': 'DAC_SYNC3',
						'P14': 'GLOBAL_PDN',
						'K14': 'FBABTDD',
						'R6': 'FBCDTDD',
						'H15': ['TXATDD','TXBTDD'],
						'V5': ['TXCTDD','TXDTDD'],
						'E7': ['RXATDD','RXBTDD'],
						'R15': ['RXCTDD','RXDTDD']}


info('')
info('************************************************************')
info('          JESD setup complete')
info('************************************************************')
info('')

step 4 script

##########              Clock distribution mode setting              ##########

setupParams.skipLmk					= 0
lmkParams.pllEn 					= (custom_clk == 0)
lmkParams.inputClk 					= f0*NinputClk
lmkParams.sysrefFreq				= lmkParams.inputClk#f0*Nrx/1024
lmkParams.lmkFrefClk				= 1
lmkParams.lmkPulseSysrefMode 		= 0
#AFE.systemStatus.sysrefFreq		= lmkParams.inputClk

lmk.rawWriteLogEn 					= 1
lmk.logEn 							= 1

logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat				= 0x01
logDumpInst.rewriteFile				= 1
logDumpInst.rewriteFileFormat4		= 1

device.optimizeWrites				= 0
device.rawWriteLogEn				= 1
device.delay_time                   = 0

if separate_runtime == 1:
	setupParams.skipLmk				= False
	AFE.initializeConfig()
	lmkParams.sysrefFreq			= AFE.systemStatus.sysrefFreq
	lmkParams.lmkPulseSysrefMode 	= 0
	AFE.LMK.lmkConfig()
	# Force Latte to program the LMK outputs (relevant to the FPGA) in bypass/distribution mode
	lmk.head.page.DCLK0_SDCLK1_controls.Analog_Dig_Delay.dclk_mux_lt_1_0_gt_=2
	lmk.head.page.DCLK8_SDCLK9_controls.Analog_Dig_Delay.dclk_mux_lt_1_0_gt_=2
	lmk.head.page.DCLK12_SDCLK13_controls.Analog_Dig_Delay.dclk_mux_lt_1_0_gt_=2
	setupParams.skipLmk				= True
	
	
info('')
info('************************************************************')
info('          LMK setup complete')
info('************************************************************')
info('')

step 6 script

AFE.deviceBringup()
AFE.TOP.overrideTdd(15,3,15)


info('')
info('************************************************************')
info('          AFE bringup complete')
info('************************************************************')
info('')

  • 0
    TI__Genius 17921 points

    Hi Željko,

     

    One thing that could cause these errors are a mismatch of the JESD parameters between the AFE and FPGA. Can you confirm that the AFE and FPGA have the F, K, and scrambling parameter the same? Also, one other thing that can be looked at is the Lane mux and lane inversions. From the AFE EVM to the FPGA dev kit the SERDES lanes polarity can be inverted. The lane polarity inversion should be taken care of either on the FPGA side or on the AFE side.

     

    In the case of JESD errors you can try the AFE.adcDacSync() command in the command line. This command will try to re-establish the JESD link.

    Regards,

    David Chaparro

  • 0 in reply to David Chaparro
    Intellectual 318 points

    Hi David,

    Thanks for the reply. Indeed, on both sides (AFE & FPGA) K is 16, F is 2, scrambling is on (set to 1). We also tried AFE.adcDacSync() upon deviceBringup failure, but to no avail, as the same alarms and errors were raised. Lane mux, inversion, and polarity we didn't check on the FPGA side, though it is specified in the AFE scripts I attached. Will look into that and report on the outcome.

    Kind regards,

    Željko

  • 0 in reply to Zeljko Jelic
    TI__Genius 17921 points

    Hi Zeljko,

    In the scripts that you attached the Lane mux and inversion are set to the default values, which would indicate that the AFE and FPGA lanes are routed one to one with no polarity inversion. I believe the main issue would be the SERDES lane polarities, as usually some of the lanes are inverted when connected to the dev kits. 

    Regards,

    David Chaparro

  • 0 in reply to David Chaparro
    Intellectual 318 points

    Hi David,

    I just got a confirmation from our FPGA designer that all the necessary lane inversions and polarities are handled already by the FPGA, and they take into account AFE routing (from the AFE schematics).

    I just realized that in the Latte code there are also two properties set to zero, namely adcDataMuxEn and dacDataMuxEn. If I were to change lane mux and inversion, do I also first need to enable these parameters?

    Additionally, I see that for both Tx and Rx there are 2 parameters, laneMux and dataMux. Could you clarify what is the difference between the two?

    Kind regards,

    Željko

  • 0 in reply to Zeljko Jelic
    TI__Genius 17921 points

    Hi Zeljko,

    The dataMux parameter allows you to mux the Rx data after the decimation block to the two JESD blocks. The laneMux on the other hand allows you to mux the JESD data to different SERDES lanes. Please see the AFE79xx Configuration Guide for additional information. 

    I tested your script on my setup and I was able to get a successful link, this was with DCLK2 as the reference to the AFE. So the issue should not be an issue with the AFE configuration. 

    One thing that could be the issue is the SYSREF signal to the AFE. Do you have SYSREF coming from SDCLK9? If so can you confirm that 'lmk.head.page.DCLK8_SDCLK9_controls.Analog_Dig_Delay.sdclk_mux' is set to '1' and measure the SYSREF frequency output on the board to verify it is the correct frequency? 

    To help debug if the issue is SYSREF related you can configure the AFE to use an internal SYSREF by setting the 'sysParams.useSpiSysref' parameter to 1. Can you give this a try in your setup?


    Regards,

    David Chaparro

  • 0 in reply to David Chaparro
    Intellectual 318 points

    Hi David,

    Thanks for the reply and clarifications.

    Can you tell me when you did the test, did you have any FPGA present in the setup, or was it another device, or was it a loopback configuration? If FPGA was there, could it be possible to share the VHDL files in that case?

    Yesterday I measured the SDCLK9 signal (SDCLKOUT9, to be more exact) and it was at 5.115 MHz, which is 163.68 divided by 32 (163.68 MHz being my external reference clock). Also the parameter you suggested to check, lmk.head.page.DCLK8_SDCLK9_controls.Analog_Dig_Delay.sdclk_mux, was by default set to 0, so I had to manually change it to 1.

    The issue persisted, however.

    BTW, if I were to enable sysParams.useSpiSysref, what will be the value of the internal SYSREF? 122.88 MHz or user defined (e.g. 163.68 MHz)?

    Kind regards,

    Željko

  • 0 in reply to Zeljko Jelic
    TI__Genius 17921 points

    Hi Zeljko,

    I would still recommend that you try the internal SYSREF. If the issue is with the timing of SYSREF then using the internal SYSREF will allow us to debug this. When using the internal SYSREF the AFE will provide a pulse during the required moments in the AFE bringup. 

    When I tested your script I used the TSW14J58 which is one of TI's data capture cards. The firmware that is installed is not available to share. If you are using the TI JESD204 IP one thing that I can try is to create reference design for the AFE79xxEVM and a Kintex 7 dev Kit and share this with you. However, this would require you to have access to the TI JESD204 IP, https://www.ti.com/tool/TI-JESD204-IP. 

    One thing I was also interested in is if the ADC link was also having similar issues. Is the ADC JESD link up and running without errors?

    Regards,

    David Chaparro

  • 0 in reply to David Chaparro
    Intellectual 318 points

    Hi David,

    Thanks for the reply.

    So, I did a test where the internal SYSREF is enabled (sysParams.useSpiSysref = 1) and this is the error log I got after running the AFE.deviceBringup() command:

    #Executing .. AFE79xx/bringup/AWS_step6_AFEbringup.py

    #Start Time 2023-04-04 10:15:29.346000

    The External Sysref Frequency should be an integer factor of: 5.115MHz

    2T2R1F Number: 0

    Valid Configuration: True

    laneRateRx: 6547.2

    laneRateFb: 6547.2

    laneRateTx: 6547.2

    2T2R1F Number: 1

    Valid Configuration: True

    laneRateRx: 6547.2

    laneRateFb: 6547.2

    laneRateTx: 6547.2

    LMK and FPGA Configured.

    DONOT_OPEN_Atharv_FULL - Device registers reset.

    chipType: 0xa

    chipId: 0x78

    chipVersion: 0x11

    AFE Reset Done

    Fuse farm load autoload done successful

    No autload error

    Fuse farm load autoload done successful

    No autload error

    //Firmware Version = 11000

    //PG Version = 1

    //Release Date [dd/mm/yy] = 10/7/19

    patchSize=11697

    //Patch Version = 165

    //PG Version = 0

    //Release Date [dd/mm/yy] = 27/11/21

    AFE MCU Wake up done and patch loaded.

    PLL Locked

    AFE PLL Configured.

    AFE SerDes Configured.

    AFE Digital Chains configured.

    AFE TX Analog configured.

    AFE RX Analog configured.

    AFE FB Analog configured.

    AFE JESD configured.

    aoc AFE JESD configured

    AFE AGC configured.

    AFE GPIO configured.

    aoc self.systemParams.executeLinkUpSequenceSeparately==False

    Sysref Read as expected

    aoc deviceBringUp() before selectCh()

    aoc selectCh() rxFbTx=2 ch_no=0 band=0 tapOff=0

    aoc selectChSilicon() before getJesdAlarms

    aoc selectChSilicon() after getJesdAlarms

    aoc selectChSilison() end

    aoc 0

    ###########Device DAC JESD-RX 0 Link Status###########

    Serdes-FIFO error for lane 0: 1

    Frame Sync error (unexpected k28.5) for lane 0: 1

    Serdes-FIFO error for lane 1: 1

    Frame Sync error (unexpected k28.5) for lane 1: 1

    Serdes-FIFO error for lane 2: 1

    Frame Sync error (unexpected k28.5) for lane 2: 1

    Serdes-FIFO error for lane 3: 1

    Frame Sync error (unexpected k28.5) for lane 3: 1

    lane0 Errors=0b11001111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; frame alignment error; multiframe alignment error;

    lane1 Errors=0b11001111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; frame alignment error; multiframe alignment error;

    lane2 Errors=0b11001111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; frame alignment error; multiframe alignment error;

    lane3 Errors=0b11001111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; frame alignment error; multiframe alignment error;

    CS State TX0: 0b00101000 . It is expected to be 0b10101010

    FS State TX0: 0b01010101 . It is expected to be 0b01010101

    Couldn't get the link up for device RX: 0; Alarms: 0xcfcfcfcff000f000L

    ###################################

    ###########Device DAC JESD-RX 1 Link Status###########

    lane0 Errors=0b0111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error;

    lane1 Errors=0b0111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error;

    lane2 Errors=0b0111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error;

    lane3 Errors=0b0111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error;

    CS State TX0: 0b10101010 . It is expected to be 0b10101010

    FS State TX0: 0b00000000 . It is expected to be 0b01010101

    Couldn't get the link up for device RX: 1; Alarms: 0x707070700000000L

    ###################################

    AFE Configuration Complete

    ************************************************************

    AFE bringup complete

    ************************************************************

    #Done executing .. AFE79xx/bringup/AWS_step6_AFEbringup.py

    #End Time 2023-04-04 10:16:08.158000

    #Execution Time = 38.8120000362 s

    #================ ERRORS:18, WARNINGS:0 ================#

    This seems to be the same set of errors as before.

    Now, about the ADC operation, from the FPGA side, up to the step 6 where the AFE.deviceBringup() is called (not including it) and after the JESD functionality reset in the FPGA we see that there is something incoming from the ADC side (there is a data counter on the FPGA side which counts incoming data chunks from the ADC). In my setup, there is an 800 MHz sinewave signal at the analog input of the ADC. However we are not sure if we see this in the FPGA.The FIFO buffer that reads the ADC data (1024 samples per lane) from all 8 lanes shows random data on lanes 0-5, while on lanes 6 and 7 there seem to be a noisy ramp-like signals (which are not identical, one is increasing and other is decreasing). Those two might be I and Q of sinewave from ADC where the 1024 samples are too short of an interval to see a sinewave character and linear approximation is thus observed.

    If at this stage I send a test ramp pattern to the FPGA from AFE JESD Tx (at ADC side), in the FPGA we can see the ramp data, 2 sets of 4 lanes with same ramp values. But, if instead of sending the ramp data I try and run the AFE.deviceBringup(), the errors from the log are raised (as shown above), and in the FPGA we see that all of the sudden incoming data is no more (data counter stops incrementing), and we see that all incoming data from the ADC at the point where data counting stopped is all zeros across all lanes (in the FPGA FIFO buffer). The only way to get the data counter unstuck is to reset the JESD interface on the FPGA side. Note that during the entire bringup procedure, we do not see any errors raised in Latte about the ADC and JESD Tx (only the ones from the log above).

    Finally, about the reference design for Kintex 7 boards, if it is possible to make it, we would greatly appreciate it, as this could be the bridge between our design and working design, so it would make the debugging significantly easier.  For the access to the TI JESD204 IP, I just requested it.

    Kind regards,

    Zeljko

  • 0 in reply to Zeljko Jelic
    TI__Genius 17921 points

    Hi Zeljko,

    For the Kintex 7 dev kit we have a KC705 in our lab. This board only has 4 of the transceiver lanes routed to the FMC connector so I would not be able to create a design for all four channels. What I can do is create the reference design with only 4 lanes and disable half of the channels on the AFE. You can then use this as a starting point for your design. 

    Would this approach still work for you?

    Regards,

    David Chaparro

  • 0 in reply to David Chaparro
    Intellectual 318 points

    Hi David,

    Just to check, in our current design we use Xilinx Kintex 7 XC7K410T, will that board be compatible with the design made on the KC705?

    Regarding the transceivers, as long as we could have at least 2 Tx and 2 Rx, then 4 lanes in total should be fine.

    Kind regards,

    Željko

  • 0 in reply to Zeljko Jelic
    Intellectual 318 points

    Hi David,

    A small question here - could it also be that these errors from my original post arise somehow due to bad GPIO pin-out mapping? 

    We made a separate setting, with AFE7950EVM and a ZC706 board (apparently we had one spare from another project), so we could use directly the TI reference design. Initially we had similar (not identical) errors when we introduced 163.68 MHz clock to the reference design (we incrementally changed the reference design of the FPGA to allow for the different clock) and then I realized that my original Latte script had different GPIO mapping from the Latte script in the reference design.

    my original GPIO mapping:

    sysParams.gpioMapping={ 'H8': 'ADC_SYNC0',

    'H7': 'ADC_SYNC1',

    'N8': 'ADC_SYNC2',

    'N7': 'ADC_SYNC3',

    'H9': 'DAC_SYNC0',

    'G9': 'DAC_SYNC1',

    'N9': 'DAC_SYNC2',

    'P9': 'DAC_SYNC3',

    'P14': 'GLOBAL_PDN',

    'K14': 'FBABTDD',

    'R6': 'FBCDTDD',

    'H15': ['TXATDD','TXBTDD'],

    'V5': ['TXCTDD','TXDTDD'],

    'E7': ['RXATDD','RXBTDD'],

    'R15': ['RXCTDD','RXDTDD']}

    GPIO mapping from the reference design:

    sysParams.gpioMapping = {

    'H8': 'ADC_SYNC0',

    'H7': 'DAC_SYNC0',

    'N8': 'ADC_SYNC2',

    'N7': 'ADC_SYNC3',

    'H9': 'ADC_SYNC1',

    'G9': 'DAC_SYNC1',

    'N9': 'DAC_SYNC2',

    'P9': 'DAC_SYNC3',

    'P14': 'GLOBAL_PDN',

    'K14': 'FBABTDD',

    'R6': 'FBCDTDD',

    'H15': ['TXATDD','TXBTDD'],

    'V5': ['TXCTDD','TXDTDD'],

    'E7': ['RXATDD','RXBTDD'],

    'R15': ['RXCTDD','RXDTDD']}

    As you can see DAC sync signals were mapped to different pins.

    Now, when I tried to use updated GPIO mapping with the script in the original post above I still got the same errors, but I am wondering if this could be that simply a different, third, version of GPIO mapping is needed here. In fact, is there a way to know somehow how FPGA and AFE should align when it comes to GPIO mapping?

    Can you comment on this, or is my reasoning here completely out of line?

    Kind regards,

    Željko

  • 0 in reply to Zeljko Jelic
    TI__Genius 17921 points

    Hi Zeljko,

    The GPIO mapping differences that you are showing are for the DAC SYNC signal. This should not be an issue as long as you specify the correct pin on the FPGA side. On our reference designs we map the DAC SYNC to pin 'H7' on the AFE and we make sure that the FPGA expects the SYNC signal on its corresponding pin. Can you verify that on your FPGA side you expect the DAC SYNC to be connected to 'H9' on the AFE. 

    In regards to the reference design for the KC705, this FPGA is similar to the one you plan to use and you should be able to use it as a reference. The files for this can be downloaded using the link below.

    Link: https://tidrive.ext.ti.com/u/_Z9fR24fXznvn19A/a4e05359-ab99-4b95-a3bf-8e0f0d8c333c?l 

    Access Code: 9DygP2D,

    Regards,

    David Chaparro