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DAC38RF82: DAC38RF82 JESD204B Frame format for for LMFSHd = 41380

mingming zhu
Prodigy 200 points

Part Number: DAC38RF82

Hi Everyone,

I want to configure the DAC to operate in signal (12bits) DAC mode. I checked the datasheet of DAC38RF82 and found a table as follows:

However, the JESD204B core in Vivado only accepts 32bits input in each JESD lane which is not divisable by 12. Can anyone tell how to arrange the data in JESD frame?

I also noticed that the JESD serial lane rate is 11250MHz if I set the DAC to operate in 3GPS, the JESD core clock is 11250MHz/40 = 281.25MHz? DAC will receive 3000/281.25 = 10.6667 samples during a FPGA clock cycle, which is not an integer. Is there anything wrong in my understanding?

    tx_tdata[ 35: 24] <= {data_A02[3:0],data_A02[7:4],data_A02[11:8]};    
    tx_tdata[ 23: 12] <= {data_A01[3:0],data_A01[7:4],data_A01[11:8]};
    tx_tdata[ 11:  0]  <= {data_A00[3:0],data_A00[7:4],data_A00[11:8]};

  • 0
    TI__Genius 11125 points

    Hi Mingming,

    The expert on this device is out of office today. We will look into this tomorrow and get back to you.

    Regards,

    Vijay

  • 0 in reply to Vijayendra Varma Siddamsetty
    TI__Mastermind 18831 points

    Hi Mingming,

    To arrange the data you will follow the JESD204B Frame format from the data sheet for the first 24 bits. For the last 8 bits you will take part of the next sample and send this frame of 32bits. This means in the next 32 bits you will have to start with the left over 4 bits of the next sample and fill in the rest of the frame with the next samples. This means that you will have to build 3 different 32bit frames in order to send the 12bit data across correctly. The pictures below may help explain this better. 

    Regards,

    David Chaparro

  • 0 in reply to David Chaparro
    Prodigy 200 points

    Thanks,How the mapping relationship is generated?Take this picture of yours，Is there a tool？Can you send me other mapping pictures?

    LMFS=2431  4831   8238

  • 0 in reply to mingming zhu
    TI__Mastermind 18831 points

    Hi Mingming, 

    We do not have a tool for generating these. To make these tables I took the data sheet JESD frame format and used that to make the 32 bit data width that the FPGA uses.

    The LMFS that you mention all have a F of 3, meaning that they have the same number of octets per frame. This means that you will follow a similar approach and build 3 different 32bit frames in order to send the 12bit data across correctly. To build the frame format you can take the JESD frame format given in the datasheet and follow the format I gave above.

    Regards,

    David Chaparro