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AFE7950: Mapping SerDes Streams to JESD204 Frame Assembly

Part Number: AFE7950

How configurable are the SerDes lanes? The datasheet says the multiplexer can map any ADC to any SerDes lanes, and lanes not being used can be powered off. If I was only using one ADC, would I be able to spread the data out over 4 or 8 JESD lanes to reduce data rate? Or am I only limited by the configurations listed in the tables? (I'm looking at the datasheet for the AFE7950-SP, AFE7950-SEP, by the way)

Thank you!

  • Hi Bill,

    One ADC data can be sent over a maximum of 4 JESD lanes. This is limited by JESD frame assembly modes available. AFE79xx also features a crossbar multiplexer that can map any particular lane data to any of the eight physical lanes. 

    Regards,

    Vijay

  • Hey Vijay,

    Thanks for the quick response!

    Just to clarify, I can use one ADC's data spread across four lanes, with the other three ADCs turned off? I ask because I think this should reduce data rate and potentially power consumption on our FPGA.

    Additionally, can you help me understand why there are limitations on the JESD frame assembly modes available? Why are the only frame assembly modes available the ones listed in the tables?

    Thanks,

    Bill

  • Hi Bill,

    Just to clarify, I can use one ADC's data spread across four lanes, with the other three ADCs turned off?

    Yes.

    I ask because I think this should reduce data rate and potentially power consumption on our FPGA.

    Using less number of SERDES lanes and powering down unused lanes generally saves more power consumption than using more lanes at lower lane rate. 

    Additionally, can you help me understand why there are limitations on the JESD frame assembly modes available? Why are the only frame assembly modes available the ones listed in the tables?

    The datasheet tables list all the modes designed in the AFE79xx. So only these modes can be used.

    Regards,

    Vijay