DAC38RF82: Serdes lane mapping

Hi, Jim :

What does "Which RX?" mean in JESD Lanes column? Could you please explain in more detail?

In addition, I still feel something wrong with your feedback above. 

In our hardware platform, lane mapping between FPGA & DAC is straight forward.

In other word, 0-0, 1-1, 2-2, 3-3, 4-4, 5-5, 6-6, 7-7. I think lane mapping should be like the below.

Please clarify my question & thanks.

Regards,

Yao-Hua

Yao-Hua,

These are the input data pins for the DAC.

Regards,

Jim

Hi, Jim :

Our own DAC board will be like the below & the serdes connection is straightforward.

(Figure 1)

I wonder why the serdes mapping in SLICE1 is in reversed order (Figure 2) and this conflict with my understanding.

I knew serdes pin assignment of DAC38RF82 is in reversed order for RX 4~7 pairs , but we have some methods to

fix this and let serdes connection (Figure 1) to be straight, so the crossbar switch of DAC38RF82 doesn't need to swap again.

(Figure 2)

In my understanding, SLICE1 mapping should be like Figure 3 for our own DAC board (not EVM board).

Is my thinking correct ?

(Figure 3)

Yao-Hua

See if the attached file helps explain this.

In each SLICE, the JESD Lanes column.pptx

Hi, Jim :

Thanks for clarification and finally i realize the serdes lane to octetpath mapping.

The last step is to confirm the DAC38RF82 register setting.

page 1 (Multi-DUC1) : 

0x4A = 0x0F03

0x5F = 0x0123

0x60 = 0x5764

page 2 (Multi-DUC2) : 

0x4A = 0xF003

0x5F = 0x4567

0x60 = 0x3210

Please help to confirm the register setting.

Thanks.

Regards,

Yao-Hua