AFE7950: What exactly is the deterministic latency?

Dhruva Anantha Datta

Part Number: AFE7950

Can anyone explain in detail what exactly is deterministic latency that is specified in the AFE, and how do we enable the continuous mode of SYSREF in subclass 1.

Explain in greater detail what will happen if there is no deterministic latency implemented, what will be the degradation in data, the time of arrival of frames is inconsistent or the packets are in time but the latency will keep changing even on a single lane?

Thanks,

over 2 years ago

+1 Vijayendra Varma Siddamsetty over 2 years ago

TI__Genius 10895 points

Hi DA,

If deterministic latency is implemented, latency from RF input to samples in FPGA (at JESD output) will remain the same across multiple power cycles and bring-ups. Default AFE configuration is in subclass 1 when using external SYSREF. Only if 'sysParams.useSpiSysref' is set to 'True', AFE will not use external SYSREF and deterministic latency will not be guaranteed.

If deterministic latency is NOT implemented, only latency will vary from across multiple power cycles and bring-ups. There will be no degradation in data and frame intervals will be consistent.

Regards,

Vijay

0 Dhruva Anantha Datta over 2 years ago in reply to Vijayendra Varma Siddamsetty

Prodigy 70 points

Thanks! it was informative.

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AFE7950: What exactly is the deterministic latency?