AFE7950EVM: Low power at DAC output

Zeljko Jelic

Part Number: AFE7950EVM

Hi Team,

During the testing of the AFE7950EVM, I've recently encountered an issue in output power.

I am running AFE7950EVM in analog repeater configuration, where at the ADC D sinewave signal at 9.5 GHz and with -10 dBm of power is brought, and DAC D output, where this input is forwarded to, has its NCO set at 9.5 GHz. The signal captured by the spectrum analyzer is in the figure below.

It seems that DAC output (with -70 dBm of power) is about 60 dB lower than what is sent on the input to the ADC, and I don't quite understand where this loss comes from.

I am using 9.5GHz as both DAC and ADC NCO frequencies as I understand that 9.5 GHz is the point to which the matching network of AFE7950EVM is designed for.

Note that no Tx/Rx DSA settings are being changed from default in the Latte script, as the Latte script just follows the analog repeater configuration.

Could you please provide some insight on this behavior?

Kind regards,

Željko

over 2 years ago

0 Vijayendra Varma Siddamsetty over 2 years ago

TI__Genius 10865 points

Hi Željko,

The output power is too low. Can you double check if you have connected to ADC D and DAC D? Can you try other channels as well?

Please share the script you used. We will verify it.

Regards,

Vijay

0 Zeljko Jelic over 2 years ago in reply to Vijayendra Varma Siddamsetty

Intellectual 318 points

Hi Vijay,

Indeed, ADC D (from external sinewave generator at -10 dBm output power) and DAC D (to the spectrum analyzer) are connected properly (no loose connection). If I try other DACs there is only noise floor on the spectrum analyzer.

Here is the code I used:

script0.py

##########               Board initialization procedure               ##########

mainWindow.clearSession()
base_directory = "C:\\Users\\laboadmin\\Documents\\Texas Instruments\\Afe79xxLatte\\projects\\AFE79xx\\bringup\\"
mainWindow.runFile(base_directory + r"setup.py")
mainWindow.runFile(base_directory + r"devInit.py")


info('')
info('************************************************************')
info('          Mandatory AFE initialization complete')
info('************************************************************')
info('')

script1.py

##########                     General settings:                     ##########

# VLBI Tx frequency plan details:
custom_clk 							= 0#2#										# Pick AFE scenario.
enableAnalogRepeater 				= True#False#								# Enable/disable AFE in analog loopback configuration (DACs transmitting from ADCs).
XbandEnable							= True#False#								# Enable/disable DAC sampling rate in X band.
dualLanePerSignal					= False#True#								# Pick 2 lanes (True) or 4 lanes (False) to transmit signal via JESD lines.
enableAdcDacSync					= True										# Enable sync signal between ADCs and DACs and FPGA by disabling LVDS sync that fixes GPIO pins.
separateLinks						= False
enableMux							= {'Tx': False, 'Rx': False}
useSpiSysref						= True#False#								# Enable (when debugging)/disable (in real operation) internal SYSREF signal.

ncoFreqModes 						= ["1KHz", "FCW"]
Fnco_tx1 							= 2245.0
Fnco_rx1							= 800.0
Fnco_tx4							= 9500#6812.5
Fnco_rx4							= 9500#637.5
syncLoopBack						= bool(1-enableAnalogRepeater)
jesdLoopbackEn 						= bool(enableAnalogRepeater)
enableLVDSsync						= bool(1-enableAdcDacSync)
fbJesdTxSyncMux						= 3 if enableLVDSsync else 1


if custom_clk == 0:
	# TI template configuration at different clock reference
	f0 								= 122.88
	Nrx								= 24
	Nddc							= 6
	Ntx 							= 4
	NFRef							= 4
	NfpgaRefClk						= 2
	NinputClk						= 12
	LMFSHdRx              			= ['44210', '44210', '44210', '44210']
	LMFSHdFb						= ['22210', '22210']
	LMFSHdTx						= ['44210', '44210', '44210', '44210']
	jesdSystemMode					= [3, 3]
elif (custom_clk == 1):
	# Desired configuration with proper data rates, sampling rates, and bandwidths
	f0 								= 163.68
	Nrx								= 18
	Nddc							= 6
	Ntx 							= 4
	NFRef							= 1
	NfpgaRefClk						= 1
	NinputClk						= 1
	LMFSHdRx              			= ['22210', '22210', '22210', '22210']
	LMFSHdFb						= ['22210', '22210']
	LMFSHdTx						= ['22210', '22210', '22210', '22210']
	jesdSystemMode					= [3, 3]
elif custom_clk == 2:
	# Symmetric JESD configuration
	f0 								= 163.68
	Nrx								= 12
	Nddc							= 6
	NFRef							= 1
	NfpgaRefClk						= 1
	NinputClk						= 1
	LMFSHdFb						= ['22210', '22210']
	Ntx 							= 5 if XbandEnable else 3
	Nlanes 							= '2' if dualLanePerSignal else '4'
	Nconv 							= Nlanes
	LMFSHdTx 						= [Nlanes+Nconv+'210']*4
	LMFSHdRx              			= LMFSHdTx
	jesdSystemMode					= [3, 3]
	
Nduc								= Nddc*Ntx
info('Tx & Rx LMFSHd settings: '+LMFSHdTx[0])


info('')
info('------------------------------------------------------------')
info('User configuration:')
if enableAnalogRepeater:
	info('     Analog repeater') 
else:
	info('     Digital repeater')
if XbandEnable:
	info('     DAC sampling in X band enabled') 
else:
	info('     DAC sampling in X band disabled')
if enableAdcDacSync:
	info('     LVDS sync disabled - ADC and DAC sync enabled') 
else:
	info('     LVDS sync enabled - ADC and DAC sync disabled')
if custom_clk:
	info('     External clock reference used: '+str(f0)+'MHz')
else:
	info('     Internal AFE clock reference used: '+str(f0)+'MHz')
info('------------------------------------------------------------')


info('')
info('************************************************************')
info('          User parametrization complete')
info('************************************************************')
info('')

script2.py

# AFE general settings
AFE.systemStatus.loadTrims			= 1
setupParams.skipFpga 				= 1
setupParams.fpgaRefClk 				= f0*NfpgaRefClk
sysParams							= AFE.systemParams
sysParams.FRef 						= f0*NFRef
sysParams.executeLinkUpSequenceSeparately = separateLinks

##########               Analog settings: AFE 79XX EVM               ##########

# General system settings	
sysParams.RRFMode   				= 0
sysParams.modeTdd					= 0
sysParams.adcSelect0				= [0, 1, 2]
sysParams.adcSelect1				= [0, 1, 2]
sysParams.useSpiSysref				= useSpiSysref
sysParams.sysrefTermination			= 0
sysParams.ncoFreqMode				= ncoFreqModes[custom_clk != 0]
sysParams.spiMode					= 1

# ADC settings
sysParams.FadcRx 					= f0*Nrx
info('ADC sampling rate: '+str(sysParams.FadcRx)+'MHz')
sysParams.rxEnable 					= [1, 1, 1, 1]
sysParams.externalClockRx 			= 0
sysParams.halfRateModeRx 			= [0, 0]
sysParams.ddcFactorRx 				= [Nddc, Nddc, Nddc, Nddc]
info('ADC down-conversion factors: '+str(sysParams.ddcFactorRx))
sysParams.numBandsRx 				= [0, 0, 0, 0]
sysParams.numRxNCO 					= 1
sysParams.ncoRxMode					= [0, 0]
sysParams.broadcastRxNcoSel			= 0
sysParams.rxNco0 					= [ [Fnco_rx1, Fnco_rx1], 
										[870.0, 870.0], 
										[637.5, 637.5], 
										[Fnco_rx4, Fnco_rx4]]
info('ADC NCOs: '+str(sysParams.rxNco0[0][0])+'MHz, '+str(sysParams.rxNco0[1][0])+'MHz, '+str(sysParams.rxNco0[2][0])+'MHz, '+str(sysParams.rxNco0[3][0])+'MHz')
sysParams.rxNco1 					= [ [Fnco_rx1, Fnco_rx1], 
										[870.0, 870.0], 
										[637.5, 637.5], 
										[Fnco_rx4, Fnco_rx4]]

# FB settings
sysParams.FadcFb					= sysParams.FadcRx
info('FB ADC sampling rate: '+str(sysParams.FadcFb)+'MHz')
sysParams.fbEnable 					= [0, 0]
sysParams.halfRateModeFb 			= [0, 0]
sysParams.ddcFactorFb 				= [Nddc, Nddc]
info('FB ADC down-conversion factors: '+str(sysParams.ddcFactorFb))
sysParams.numBandsFb				= [0, 0]
sysParams.numFbNCO 					= 1
sysParams.ncoFbMode					= 0
sysParams.fbNco0 					= [1000, 1000]
sysParams.fbNco1 					= [1000, 1000]
sysParams.fbNco2 					= [1000, 1000]
sysParams.fbNco3 					= [1000, 1000]
info('FB ADC NCOs: '+str(sysParams.fbNco0[0])+'MHz, '+str(sysParams.fbNco1[0])+'MHz')

# DAC settings
# DAC sampling rate must fall into one of the following frequency ranges (due to pll restrictions): [7.2 GHz, 7.68 GHz] or [8.8 GHz, 9.1 GHz] or [9.7 GHz, 10.24 GHz] or [11.6 GHz, 12.08 GHz]
sysParams.Fdac 						= sysParams.FadcRx*Ntx
info('DAC sampling rate: '+str(sysParams.Fdac)+'MHz')
sysParams.txEnable 					= [1, 1, 1, 1]
sysParams.externalClockTx			= 0
sysParams.halfRateModeTx 			= [0, 0]
sysParams.ducFactorTx 				= [Nduc, Nduc, Nduc, Nduc]
info('DAC up-conversion factors: '+str(sysParams.ducFactorTx))
sysParams.numBandsTx 				= [0, 0, 0, 0]
sysParams.numTxNCO 					= 1
sysParams.combineDucMode 			= [0, 0]
sysParams.enableDacInterleavedMode 	= 0
sysParams.ncoTxMode					= [0, 0]
sysParams.broadcastTxNcoSel			= 0
sysParams.txNco0	 				= [ [Fnco_tx1, Fnco_tx1],
										[5020.0, 5020.0], 
										[8212.5, 8212.5], 
										[Fnco_tx4, Fnco_tx4]]
sysParams.txNco1 					= [ [Fnco_tx1, Fnco_tx1],
										[5020.0, 5020.0], 
										[8212.5, 8212.5], 
										[Fnco_tx4, Fnco_tx4]]
info('DAC NCOs: '+str(sysParams.txNco0[0][0])+'MHz, '+str(sysParams.txNco0[1][0])+'MHz, '+str(sysParams.txNco0[2][0])+'MHz, '+str(sysParams.txNco0[3][0])+'MHz')


info('')
info('************************************************************')
info('          Analog front end setup complete')
info('************************************************************')
info('')

script3.py

##########               JESD204 settings AFE 79XX EVM               ##########

sysParams.topLevelSystemMode		= 'StaticTDDMode'
sysParams.jesdSystemMode			= jesdSystemMode
sysParams.serdesFirmware			= 1
sysParams.jesdABLvdsSync			= enableLVDSsync
sysParams.jesdCDLvdsSync			= enableLVDSsync
sysParams.syncLoopBack				= syncLoopBack
sysParams.jesdLoopbackEn			= jesdLoopbackEn
	
	
sysParams.LMFSHdRx					= LMFSHdRx
sysParams.jesdRxProtocol			= [0, 0]
sysParams.jesdRxLaneMux				= [0, 1, 2, 3, 4, 5, 6, 7]
sysParams.jesdRxRbd					= [4, 4]
sysParams.rxJesdTxScr				= [1, 1, 1, 1]
sysParams.rxJesdTxK					= [16, 16, 16, 16]
sysParams.rxJesdTxSyncMux			= [0, 0, 0, 0]
sysParams.rxDataMux					= [0, 1, 2, 3, 4, 5, 6, 7]
sysParams.serdesRxLanePolarity		= [0, 0, 0, 0, 0, 0, 0, 0]
sysParams.adcDataMuxEn				= enableMux['Tx']
	
	
sysParams.LMFSHdFb					= LMFSHdFb
sysParams.fbJesdTxScr				= [1, 1]
sysParams.fbJesdTxK					= [16, 16]
sysParams.fbJesdTxSyncMux			= [fbJesdTxSyncMux, fbJesdTxSyncMux]
sysParams.fbDataMux					= [0, 1]
	
	
sysParams.LMFSHdTx					= LMFSHdTx
sysParams.jesdTxProtocol			= [0, 0]
sysParams.jesdTxLaneMux				= [0, 1, 2, 3, 4, 5, 6, 7]
#sysParams.jesdTxRbd					= [4, 4]
sysParams.jesdRxScr					= [1, 1, 1, 1]
sysParams.jesdRxK					= [16, 16, 16, 16]
sysParams.jesdRxSyncMux				= [0, 0, 0, 0]
sysParams.txDataMux					= [0, 1, 2, 3, 4, 5, 6, 7]
sysParams.serdesTxLanePolarity		= [0, 0, 0, 0, 0, 0, 0, 0]
sysParams.dacDataMuxEn				= enableMux['Rx']
#sysParams.serdesTxPreCursor			= [6, 6, 6, 6, 6, 6, 6, 6]
#sysParams.serdesTxPostCursor		= [0, 0, 0, 0, 0, 0, 0, 0]
#sysParams.serdesTxMainCursor		= [3, 0, 0, 0, 0, 0, 0, 3]
sysParams.setIlaParams				= 1
sysParams.jesdTxIlaM				= [8, 8, 2, 8, 8, 2]
sysParams.jesdTxIlaLid				= [0, 1, 2, 3, 4, 5, 6, 7]
sysParams.jesdTxIlaL				= [4, 4, 2, 4, 4, 2]


##########                         Dummy txt                         ##########

sysParams.gpioMapping={ 'H8': 'ADC_SYNC0',
						'H7': 'ADC_SYNC1',
						'N8': 'ADC_SYNC2',
						'N7': 'ADC_SYNC3',
						'H9': 'DAC_SYNC0',
						'G9': 'DAC_SYNC1',
						'N9': 'DAC_SYNC2',
						'P9': 'DAC_SYNC3',
						'P14': 'GLOBAL_PDN',
						'K14': 'FBABTDD',
						'R6': 'FBCDTDD',
						'H15': ['TXATDD','TXBTDD'],
						'V5': ['TXCTDD','TXDTDD'],
						'E7': ['RXATDD','RXBTDD'],
						'R15': ['RXCTDD','RXDTDD']}


info('')
info('************************************************************')
info('          JESD setup complete')
info('************************************************************')
info('')

script4.py

##########              Clock distribution mode setting              ##########

setupParams.skipLmk					= 0
lmkParams.pllEn 					= (custom_clk == 0)
lmkParams.inputClk 					= f0*NinputClk
lmkParams.sysrefFreq				= lmkParams.inputClk#f0*Nrx/1024
lmkParams.lmkFrefClk				= 1
lmkParams.lmkPulseSysrefMode 		= 0
#AFE.systemStatus.sysrefFreq		= lmkParams.inputClk

lmk.rawWriteLogEn 					= 1
lmk.logEn 							= 1

logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat				= 0x01
logDumpInst.rewriteFile				= 1
logDumpInst.rewriteFileFormat4		= 1

device.optimizeWrites				= 0
device.rawWriteLogEn				= 1
device.delay_time                   = 0

setupParams.skipLmk				= False
AFE.initializeConfig()
lmkParams.sysrefFreq			= AFE.systemStatus.sysrefFreq
lmkParams.lmkPulseSysrefMode 	= 0
AFE.LMK.lmkConfig()
# Force Latte to program the LMK outputs (relevant to the FPGA) in bypass/distribution mode
lmk.head.page.DCLK0_SDCLK1_controls.Analog_Dig_Delay.dclk_mux_lt_1_0_gt_=2
lmk.head.page.DCLK8_SDCLK9_controls.Analog_Dig_Delay.dclk_mux_lt_1_0_gt_=2
lmk.head.page.DCLK8_SDCLK9_controls.Analog_Dig_Delay.sdclk_mux=1
lmk.head.page.DCLK12_SDCLK13_controls.Analog_Dig_Delay.dclk_mux_lt_1_0_gt_=2
setupParams.skipLmk				= True
	
	
info('')
info('************************************************************')
info('          LMK setup complete')
info('************************************************************')
info('')

'''
AFE7920EVM has enabled wire-probes on the following LMK outputs:
- DCLKOUT0  (C275): thick, yellow
- SDCLKOUT1 (R353): thick, light green
- DCLKOUT2  (R345): thin, 
- SDCLKOUT3 (R352): thin, 
- SDCLKOUT9 (C259): thick, red
'''

script5.py

AFE.deviceBringup()
AFE.TOP.overrideTdd(15,3,15)


info('')
info('************************************************************')
info('          AFE bringup complete')
info('************************************************************')
info('')

Kind regards,

Željko

0 Vijayendra Varma Siddamsetty over 2 years ago in reply to Zeljko Jelic

TI__Genius 10865 points

Hi Željko,

We will run these scripts and verify functionality in our lab. Can you check connecting to other Rx and Tx pairs and see if you get expected output? For example, if input is connected to RxA, do you get expected output from TxA? Note that input frequency should be adjusted based on NCO of those channels.

Regards,

Vijay

0 David Chaparro over 2 years ago in reply to Vijayendra Varma Siddamsetty

TI__Genius 17891 points

Hi Zeljko,

I have tested your script on our setup, with minor changes to the clock settings as your LMK outputs are different, and I was able to get an output on TXD. For this setup my input to RxD was set to 9.52GHz, 0dBm, and the output that I see an output of 9.52GHz on TxD. Please try this same input on your setup.

One thing to note on your setup is that the LMK clock output for the AFE should not be in bypass mode for your 'custom_clk==0' configuration as this mode is using the LMK PLL. With the LMK PLL being used the LMK output for the AFE should be set to divider mode with a divider value of 6 in order to provide the 491.52MHz reference clock.

Regards,

David Chaparro

RF & microwave

RF & microwave forum

AFE7950EVM: Low power at DAC output