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AFE7900EVM: Whether a reset signal is required when interacting with the FPGA

wang yizhuo
Prodigy 105 points
Part Number: AFE7900EVM

Hi everyone,

I want to send data to the DAC using FPGA,In my understanding, I need a reset signal to the FPGA that my link has been set up to allow him to send data.

I found resetZ in the datasheet,But it seems to be an input signal?And the reset_FPGA interface with FMC doesn't seem to work.

I attach the related pictures below.I hope I can get some answers

  • +1
    TI__Genius 17901 points

    Hi Wang,

    The RESETZ pin can be connected to the FPGA but on the EVM it is not a requirement to get a DAC output as this is also controlled onboard by the FTDI chip. The pins that you will need connected are FPGA clocks, SERDES lanes, and SYSREF. If you are using 8b10b encoding then you will also need the SYNC IN and SYNC OUT pins, in order to establish the JESD link and start sending/receiving data. 

    Regards,

    David Chaparro