I find that there are 12 bit DACs/ADCs and the data seen on the JESD lanes is default 16bit. I wish to know what to expect from a configuration of the lanes.
Let us presume I have allocated 1RX lane to 1JESD lane and similarly the TX path, what is the order of bits and the conversion that is connected to the DSA, I was trying to understand the datasheet but it was not complete.