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AFE7950: How is the 12bit data converted to 16bit?

Part Number: AFE7950

I find that there are 12 bit DACs/ADCs and the data seen on the JESD lanes is default 16bit. I wish to know what to expect from a configuration of the lanes.

Let us presume I have allocated 1RX lane to 1JESD lane and similarly the TX path, what is the order of bits and the conversion that is connected to the DSA, I was trying to understand the datasheet but it was not complete.

  • Hi Dhruva Anantha,

    The RF DAC and ADC resolution is 14 bits. But input to DUC blocks and output from DDC blocks has 16-bit resolution. This is to accommodate higher SNR before interpolation (in RF TX signal chain) and after decimation (in RF RX signal chain).  

    When 1RX complex output data (both I and Q channels) is on one JESD lane, frame format will be as shown below:

    Regards,

    Vijay

  • Pardon me for the wrong resolution number.

    So the interpolation blocks are being provided with a 16 bit value, may I understand how is this generated from the 14bit value sampled? as I was able to go through the datasheet to notice a FP conversion for a particular DSA value.

    I was not very clear on if I should consider the FP or should I just consider the TX1_i0 and TX1_q0 as signed integers? I am not altering any DSA settings, they are in default as of now.

  • Hi Dhruva Anantha,

    In Tx signal chain, input from JESD block is has 16-bit resolution. But output of interpolation block is rounded to 14-bit resolution before sending to RF DAC. 

    In Rx signal chain, output of RF ADC has 14-bit resolution. But output of DDC has 16-bit resolution. As SNR is higher after decimation, higher resolution is used. 

    Floating point mode is only used when using internal AGC mode in Rx chain. If you don't plan on using DSA or AGC, output format will be 16-bit signed integer.  

    Regards,

    Vijay