Hi sir ,
Validating AFE7950EVM using KCU105 Eval Board.
DAC Output is not Proper, Please Refer below image.
* Both RX and TX JESD links are Up .
* Configuration used LMFS-2881, single Band Mode, No of LINKs used -1
* Generating Frequency FPGA side is 30MHz and txNCO is 1GHz
* Data Format used 2881
*To Verify the Data Format, Sent Ramp Data in RX lanes, unable to see the RAMP in RXDATA, by changing the lanes also checked
Can you please solve this problem ?
'''
Validation : AFE79xx Library Version
v1.67, v1.74
sysParams.__init__();sysParams.chipVersion=chipVersion # Set sysParms to default
setupParams.skipFpga = 1
sysParams = AFE.systemParams
setupParams.fpgaRefClk = 122.88#184.32#
AFE.systemStatus.loadTrims = 1
sysParams.fbEnable = [False]*2
sysParams.externalClockTx = False
sysParams.externalClockRx = False
sysParams.FRef = 491.52
sysParams.FadcRx = 2949.12
sysParams.FadcFb = 2949.12
sysParams.Fdac = 2949.12*4
sysParams.enableDacInterleavedMode = True #DAC interleave mode to save power consumption. Fs/2 - Fin spur occurs
sysParams.modeTdd = 0
# 0- Single TDD Pin for all Channels
# 1- Separate Control for 2T/2R/1F
# 2- Separate Control for 1T/1R/1F
sysParams.RRFMode = 0 #4T4R2F FDD mode
sysParams.jesdSystemMode = [3,3]
#SystemMode 0: 2R1F-FDD ; rx1-rx2-fb-fb
#SystemMode 1: 1R1F-FDD ; rx1-rx1-fb-fb
#SystemMode 2: 2R-FDD ; rx1-rx1-rx2-rx2
#SystemMode 3: 1R ; rx1-rx1-rx1-rx1
#SystemMode 4: 1F ; fb-fb-fb-fb
#SystemMode 5: 1R1F-TDD ; rx1/fb-rx1/fb-rx1/fb-rx1/fb
#SystemMode 8: 1R1F-TDD 1R-FDD (FB-2Lanes)(RX1 RX2 interchanged) ; rx2/fb-rx2/fb-rx1-rx1
sysParams.jesdLoopbackEn = 0 #Make it 1 to Enable the JESDTX to JESDRX internal loopback
sysParams.LMFSHdRx = ["28810","28810","28810","28810"]
# The 2nd and 4th are valid only for jesdSystemMode values in (2,6,7,8). For other modes, select 4 converter modes for 1st and 3rd.
sysParams.LMFSHdFb = ["22210","22210"]
sysParams.LMFSHdTx = ["28810","28810","28810","28810"]
sysParams.jesdTxProtocol = [0,0]
sysParams.jesdRxProtocol = [0,0]
sysParams.serdesFirmware = True # If you want to lead any firmware, please speify the path here. Otherwise it will not write any firmware
sysParams.jesdTxLaneMux = [0,1,2,3,4,5,6,7]
# Enter which lanes you want in each location.
# Note that across 2T Mux is not possible in 0.5.
# For example, if you want to exchange the first two lines of each 2T, this should be [[1,0,2,3],[5,4,6,7]]
sysParams.serdesTxLanePolarity = [False]*8
sysParams.jesdRxLaneMux = [0,1,2,3,4,5,6,7] #[0,1,2,3,4,5,7,6]
# Enter which lanes you want in each location.
# Note that across 2R Mux is not possible in 0.5.
# For example, if you want to exchange the first two lines of each 2R, this should be [[1,0,2,3],[5,4,6,7]]
sysParams.serdesRxLanePolarity = [False]*8
sysParams.jesdRxRbd = [4, 4]
sysParams.rxJesdTxScr = [True]*4
sysParams.fbJesdTxScr = [True]*2
sysParams.jesdRxScr = [True]*4
sysParams.rxJesdTxK = [16]*4
sysParams.fbJesdTxK = [16]*2
sysParams.jesdRxK = [16]*4
sysParams.ncoFreqMode = "1KHz"
sysParams.txNco0 = [[1000,1800], #Band0, Band1 for TxA for NCO0
[1000,1800], #Band0, Band1 for TxB for NCO0
[1000,1800], #Band0, Band1 for TxC for NCO0
[1000,1800]] #Band0, Band1 for TxD for NCO0
sysParams.rxNco0 = [[1000,1800], #Band0, Band1 for RxA for NCO0
[1000,1800], #Band0, Band1 for RxB for NCO0
[1000,1800], #Band0, Band1 for RxC for NCO0
[1000,1800]] #Band0, Band1 for RxD for NCO0
sysParams.fbNco0 = [500,1800] #FBA, FBC for NCO0
sysParams.numBandsRx = [0]*4 # 0 for single, 1 for dual
sysParams.numBandsFb = [0,0]
sysParams.numBandsTx = [0,0,0,0]
sysParams.ddcFactorRx = [6*4]*4 # DDC decimation factor for RX A, B, C and D
sysParams.ddcFactorFb = [6*4]*4
sysParams.ducFactorTx = [24*4]*4
## The following parameters sets up the LMK04828 clocking schemes
lmkParams.pllEn = True#False
lmkParams.inputClk = 1474.56#737.28
lmkParams.sysrefFreq = 2949.12/1024
lmkParams.lmkFrefClk = True
## The following parameters sets up the register and macro dumps
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat = 0x0
logDumpInst.rewriteFile = 1
logDumpInst.rewriteFileFormat4 = 1
device.optimizeWrites = 0
device.rawWriteLogEn = 1
lmk.rawWriteLogEn = 1
## The following parameters sets up the SYNCIN and SYNCOUT to interface with the TSW14J57
sysParams.jesdABLvdsSync = 0
sysParams.jesdCDLvdsSync = 0
sysParams.rxJesdTxSyncMux = [0,0,0,0]
sysParams.fbJesdTxSyncMux = [0,0]
sysParams.jesdRxSyncMux = [0,0,0,0] #[0,0,1,1]
sysParams.syncLoopBack = True
## The following parameters sets up the GPIOs
sysParams.gpioMapping={
'H8': 'ADC_SYNC0',
'H7': 'DAC_SYNC0',
'N8': 'ADC_SYNC2',
'N7': 'ADC_SYNC3',
'H9': 'ADC_SYNC1',
'G9': 'DAC_SYNC1',
'N9': 'DAC_SYNC2',
'P9': 'DAC_SYNC3',
'P14': 'GLOBAL_PDN',
'K14': 'FBABTDD',
'R6': 'FBCDTDD',
'H15': ['TXATDD','TXBTDD'],
'V5': ['TXCTDD','TXDTDD'],
'E7': ['RXATDD','RXBTDD'],
'R15': ['RXCTDD','RXDTDD']}
device.delay_time=0
setupParams.skipLmk = False
AFE.initializeConfig()
lmkParams.sysrefFreq = AFE.systemStatus.sysrefFreq
lmkParams.lmkPulseSysrefMode = False
AFE.LMK.lmkConfig()
## Initiates AFE79xx Bring-up setupParams.skipLmk = True AFE.deviceBringup() AFE.TOP.overrideTdd(15,0,15) for i in range(4): AFE.DSA.setRxDsa(i,4) ### for ADC Ramp Out for i in range(3): AFE.JESD.ADCJESD[0].adcRampTestPattern(i,1,1) AFE.JESD.ADCJESD[1].adcRampTestPattern(i,1,1) #chNo, En, RampInc
can you please verify AFE LMK code?
Regards ,
Krishnaveni
