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AFE7950: JESD204 setting

David Park
Expert 6730 points
Part Number: AFE7950

Hi,

Customer would like to set JESD204 for 1 TX DAC on 4 lanes and it means 4211.

it can be below setting.

Lane 0: I[15:8]

Lane 1: I[7:0]

Lane 2: Q[15:8]

Lane 3: Q[7:0]

Customer wants to use 1500Mbps for input bitrate but can't find this setting in Table 8.12.

Could you guide for it?

Thanks.

  • 0
    TI__Genius 10865 points

    Hi David,

    Though it's not shown in Table 8-12, AFE supports 4211 at 1500MSPS input rate. SERDES lane rate in this case will be 15Gbps (assuming 8b/10b encoding).

    Also note that LMFS 4422 supports the same rates with samples not split across SERDES lanes. This is easier to handle in FPGA  ADC capture firmware when compared to LMFS: 4211. 

    Frame format for LMFS 4422 is as below:

    Lane 0: I_S0[15:0]

    Lane 1: I_S1[15:0]

    Lane 2: Q_S0[15:0]

    Lane 3: Q_S1[15:0]

    Regards,

    Vijay