Hello,
My customer to would like to connect two AFE7906s with a Xilinx FPGA via 8 lanes (4 lanes for each AFE7906).
At each AFE7906, FB ADCs are not used and only 4x RX ADCs are used.
Each RX ADC configuration is as follows.
ADC sampling rate = 1536MSPS
Decimation = 6x
Baseband sampling rate = 256MSPS
Baseband data resolution = 16bit
JESD encoding = 8/10b
JESD format = 48410
JESD SerDes rate = 10240Mbps
Here, they have some questions.
Q1:
No issues at their usage above?
Q2:
Which FPGA JESD IP should be used, 2x 4 lanes or 1x 8 lanes?
Q3:
If TI has example of connecting two AFEs with one Xilinx FPGA, pleas introduce the information about it.
Best regards,
K.Hirano
