• State Resolved
  • Locked Locked
  • Replies 7 replies
  • Answers 2 answers
  • Subscribers 11 subscribers
  • Views 870 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AFE7900: Mapping table with AFE7900's LMFS vs JESD204B and its LINE DATA WIDTH(32/64BIT)

MINGFENG YANG
Prodigy 30 points
Part Number: AFE7900

Do you have mapping table with AFE7900's LMFS vs JESD204B and its LINE DATA WIDTH(32/64BIT)?
Currently using TI-204C IP on the FPGA side, but I don't know what to do Mapping (DAC/ADC) IQ data.

  • 0
    TI__Genius 10865 points

    Hi Mingfeng,

    What is the LMFS for the JESD mode you are using? For a given LMFS, there's only one possible frame format as per JESD204C specification. When using the TI JESD IP, LANE_DATA_WIDTH is set by 'RX_LN_DATA_WIDTH' and 'TX_LN_DATA_WIDTH' parameters of 204C-IP. This is set to 64 by default. Refer to the IP user guide for more info.

    Frame formats for some commonly used modes:

    Regards,

    Vijay

  • 0 in reply to Vijayendra Varma Siddamsetty
    Prodigy 30 points

    My JESD & LMFS mode is JESD204B/24410,I split the problem into three item:

    1.If setting TX_LN_DATA_WIDTH is 32bit,What is the arrangement relationship of tx1_i0[15:0], tx1_q0[15:0] in tx_lane_data[31:0]?

    2.If setting TX_LN_DATA_WIDTH is 64bit,What is the arrangement relationship of tx1_i0[15:0], tx1_q0[15:0] in tx_lane_data[63:0]?

    3.AFE7900 is 14bit's DAC/ADC.How do I arrange 14bit' IQ data in 16bit's line data?example:assign tx1_i0[15:0] = {I[13:0],2'b0}; or assign tx1_i0[15:0] = {2'b0,I[13:0]};

    Thank you!!

  • 0 in reply to MINGFENG YANG
    TI__Genius 10865 points

    Hi Mingfeng,

    1. As the frame in 24410 mode is 32 bit wide, LN_DATA_WIDTH is set to 32, there will be one frame data in tx_lane_data[31:0].

    2. If LN_DATA_WIDTH is set to 64, there will be two frame data in tx_lane_data[63:0].

    3. As shown in the frame format, complex data samples at JESD interface are 16-bit wide. 

    In Tx signal chain, input from JESD block is has 16-bit resolution. But output of interpolation block is rounded to 14-bit resolution before sending to RF DAC. 

    In Rx signal chain, output of RF ADC has 14-bit resolution. But output of DDC has 16-bit resolution. As SNR is higher after decimation, higher resolution is used. 

    Regards,

    Vijay

  • +1 in reply to MINGFENG YANG
    TI__Genius 17871 points

    Hi Mingfeng,

    1. If the lane data width is 32 bit then the arrangement will look exactly like Vijay shows above for 24410

    2. If the lane data width is 64 then you get two samples on a lane for each channel and the frame format will look like the below.

    3. The AFE JESD block is configured for 16 bit so the inputs and outputs should be given or received as 16 bit samples. This means that in the FPGA you should use a resolution of 16 bit. 

    Regards,

    David Chaparro

  • 0 in reply to David Chaparro
    Prodigy 30 points 

    hello I understand question 3, but I can't open the pictures of questions 1 and 2. Could you please upload it again? Thank you
  • +1 in reply to MINGFENG YANG
    TI__Genius 17871 points

    Hi Mingfeng,

    Please see my previous reply for fixed images.

    Regards,

    David Chaparro

  • 0 in reply to David Chaparro
    Prodigy 30 points

    OK,I understand.Thank you