AFE7950: Device clock and SYSREF path length

Hi,

Customer is designing AFE7950 and LMK04832 for satellite communication payload.

Device clock and SYSREF path length is same for AFE7950 and device clock and SYSREF path length is same for FPGA.

However path length from clock to AFE7950 and path length from clock to FPGA is different.

Is it ok? If yes, please let me know how many difference is acceptable.

Now 

Jitter cleaner to FPGA length: 138 mm

Jitter cleaner to AFE7950 length: 42.6 mm

Thanks.