Other Parts Discussed in Thread: AFE7950,
Dear engineer from TI,
I tried to use the TI's AFE7950EVM board and Xinlinx's ACU128 FPGA to do the ADC/DAC processing. But I failed. I think there are two possible problems. One is the Latte configuration of AFE7950. The latte program I have used and the log error are in the followings, I have no idea how th deal with the error because it didn't work after I change the rbd value. I don't think this has anything to do with FPGAs. Could you please try this latte program on the AFE7950EVM to see what the problem is and how can I modify it to run correctly?
sysParams.__init__();sysParams.chipVersion=chipVersion # Set sysParms to default
setupParams.skipFpga = 1
sysParams = AFE.systemParams
AFE.systemStatus.loadTrims = 1
sysParams.fbEnable = [False]*2
sysParams.externalClockTx = False
sysParams.externalClockRx = False
sysParams.FRef = 491.52
sysParams.FadcRx = 2949.12
sysParams.FadcFb = 2949.12
sysParams.Fdac = 2949.12*4
sysParams.enableDacInterleavedMode = False #DAC interleave mode to save power consumption. Fs/2 - Fin spur occurs
sysParams.modeTdd = 0
# 0- Single TDD Pin for all Channels
# 1- Separate Control for 2T/2R/1F
# 2- Separate Control for 1T/1R/1F
sysParams.RRFMode = 0 #4T4R2F FDD mode
sysParams.jesdSystemMode = [3,3]
#SystemMode 0: 2R1F-FDD ; rx1-rx2-fb-fb
#SystemMode 1: 1R1F-FDD ; rx1-rx1-fb-fb
#SystemMode 2: 2R-FDD ; rx1-rx1-rx2-rx2
#SystemMode 3: 1R ; rx1-rx1-rx1-rx1
#SystemMode 4: 1F ; fb-fb-fb-fb
#SystemMode 5: 1R1F-TDD ; rx1/fb-rx1/fb-rx1/fb-rx1/fb
#SystemMode 8: 1R1F-TDD 1R-FDD (FB-2Lanes)(RX1 RX2 interchanged) ; rx2/fb-rx2/fb-rx1-rx1
sysParams.jesdLoopbackEn = 1 #Make it 1 to Enable the JESDTX to JESDRX internal loopback
sysParams.LMFSHdRx = ["44210","44210","44210","44210"]
# The 2nd and 4th are valid only for jesdSystemMode values in (2,6,7,8). For other modes, select 4 converter modes for 1st and 3rd.
sysParams.LMFSHdFb = ["22210","22210"]
sysParams.LMFSHdTx = ["44210","44210","44210","44210"]
sysParams.jesdTxProtocol = [2,2]
sysParams.jesdRxProtocol = [2,2]
sysParams.serdesFirmware = True # If you want to lead any firmware, please speify the path here. Otherwise it will not write any firmware
sysParams.jesdTxLaneMux = [0,1,2,3,4,5,6,7]
# Enter which lanes you want in each location.
# Note that across 2T Mux is not possible in 0.5.
# For example, if you want to exchange the first two lines of each 2T, this should be [[1,0,2,3],[5,4,6,7]]
sysParams.serdesTxLanePolarity = [False]*8
sysParams.jesdRxLaneMux = [0,1,2,3,4,5,6,7] #[0,1,2,3,4,5,7,6]
# Enter which lanes you want in each location.
# Note that across 2R Mux is not possible in 0.5.
# For example, if you want to exchange the first two lines of each 2R, this should be [[1,0,2,3],[5,4,6,7]]
sysParams.serdesRxLanePolarity = [False]*8
sysParams.jesdRxRbd = [28,28]
sysParams.jesdTxRbd = [28,28]
sysParams.rxJesdTxScr = [False]*4
sysParams.fbJesdTxScr = [False]*2
sysParams.jesdRxScr = [False]*4
sysParams.rxJesdTxK = [32]*4
sysParams.fbJesdTxK = [32]*2
sysParams.jesdRxK = [32]*4
sysParams.ncoFreqMode ="1KHz" #"FCW"
##### RX #####
sysParams.ddcFactorRx = [6,6,6,6] #DDC decimation factor for RX A, B, C and D
sysParams.rxNco0 = [[9500,9500], #Band0, Band1 for RXA
[9500,9500], #Band0, Band1 for RXB
[9500,9500], #Band0, Band1 for RXC
[9500,9500]] #Band0, Band1 for RXD
##### TX #####
sysParams.txEnable = [True,True,True,True]
sysParams.ducFactorTx = [24,24,24,24] #DUC interpolation factor for TX A, B, C and D
sysParams.txNco0 = [[9500,9500], #Band0, Band1 for TXA
[9500,9500], #Band0, Band1 for TXB
[9500,9500], #Band0, Band1 for TXC
[9500,9500]] #Band0, Band1 for TXD
sysParams.numBandsRx = [0]*4 # 0 for single, 1 for dual
sysParams.numBandsFb = [0,0]
sysParams.numBandsTx = [0]*4
## The following parameters sets up the LMK04828 clocking schemes
lmkParams.pllEn = True#False #
lmkParams.inputClk = 983.04 # Valid only when lmkParams.pllEn = False
lmkParams.lmkFrefClk = True
setupParams.fpgaRefClk = 122.88 # Should be equal to LaneRate/40
## The following parameters sets up the SYNCIN and SYNCOUT to interface with the TSW14J57
sysParams.jesdABLvdsSync = True
sysParams.jesdCDLvdsSync = True
sysParams.rxJesdTxSyncMux = [0,0,0,0]
sysParams.fbJesdTxSyncMux = [0,0]
sysParams.jesdRxSyncMux = [0,0,0,0] #[0,0,1,1]
sysParams.syncLoopBack = True
sysParams.gpioMapping = {
'H8': 'ADC_SYNC0',
'H7': 'ADC_SYNC1',
'N8': 'DAC_SYNC0',
'N7': 'DAC_SYNC1',
'H9': 'ADC_SYNC2',
'G9': 'ADC_SYNC3',
'N9': 'DAC_SYNC2',
'P9': 'DAC_SYNC3',
'P14': 'GLOBAL_PDN',
'K14': 'FBABTDD',
'R6': 'FBCDTDD',
'H15': ['TXATDD','TXBTDD'],
'V5': ['TXCTDD','TXDTDD'],
'E7': ['RXATDD','RXBTDD'],
'R15': ['RXCTDD','RXDTDD']}
device.delay_time=0
AFE.initializeConfig()
lmkParams.sysrefFreq = AFE.systemStatus.sysrefFreq
lmkParams.lmkPulseSysrefMode = False
AFE.LMK.lmkConfig()
AFE.TOP.sendSysref(1)
AFE.adcDacSync()
setupParams.skipLmk = True
AFE.deviceBringup()
AFE.TOP.overrideTdd(15,3,15)
#======
#Executing .. AFE7950/bringup/script14.py
#Start Time 2023-06-26 10:05:26.988000
The External Sysref Frequency should be an integer factor of: 1.28MHz
2T2R1F Number: 0
Valid Configuration: True
laneRateRx: 8110.08
laneRateFb: 8110.08
laneRateTx: 8110.08
2T2R1F Number: 1
Valid Configuration: True
laneRateRx: 8110.08
laneRateFb: 8110.08
laneRateTx: 8110.08
SPIA has got control of PLL pages
PLL Pages SPI control relinquished.
SPIA has got control of PLL pages
PLL Pages SPI control relinquished.
###########Device DAC JESD-RX 0 Link Status###########
lane0 Errors=0b10000; Got errors: elastic buffer overflow (bad RBD value);
lane1 Errors=0b10000; Got errors: elastic buffer overflow (bad RBD value);
lane2 Errors=0b10000; Got errors: elastic buffer overflow (bad RBD value);
lane3 Errors=0b10000; Got errors: elastic buffer overflow (bad RBD value);
CS State TX0: 0b10101010 . It is expected to be 0b10101010
BUF State TX0: 0b11111111 . It is expected to be 0b11111111
Couldn't get the link up for device RX: 0; Alarms: 0x1010101000000000L
###################################
###########Device DAC JESD-RX 1 Link Status###########
lane0 Errors=0b10000; Got errors: elastic buffer overflow (bad RBD value);
lane1 Errors=0b10000; Got errors: elastic buffer overflow (bad RBD value);
lane2 Errors=0b10000; Got errors: elastic buffer overflow (bad RBD value);
lane3 Errors=0b10000; Got errors: elastic buffer overflow (bad RBD value);
CS State TX0: 0b10101010 . It is expected to be 0b10101010
BUF State TX0: 0b11111111 . It is expected to be 0b11111111
Couldn't get the link up for device RX: 1; Alarms: 0x1010101000000000L
###################################
The External Sysref Frequency should be an integer factor of: 1.28MHz
2T2R1F Number: 0
Valid Configuration: True
laneRateRx: 8110.08
laneRateFb: 8110.08
laneRateTx: 8110.08
2T2R1F Number: 1
Valid Configuration: True
laneRateRx: 8110.08
laneRateFb: 8110.08
laneRateTx: 8110.08
Device Initialization for ChipVersion: 1.3
DONOT_OPEN_Atharv_FULL - Device registers reset.
chipType: 0xa
chipId: 0x78
chipVersion: 0x11
SPIA has got control of PLL pages
PLL Pages SPI control relinquished.
Fuse farm load autoload done successful
No autload error
Fuse farm load autoload done successful
No autload error
//Firmware Version = 11000
//PG Version = 1
//Release Date [dd/mm/yy] = 10/7/19
patchSize=11697
//Patch Version = 165
//PG Version = 0
//Release Date [dd/mm/yy] = 27/11/21
SPIA has got control of PLL pages
PLL Locked
PLL Pages SPI control relinquished.
SPIA has got control of PLL pages
PLL Pages SPI control relinquished.
SPIA has got control of PLL pages
PLL Pages SPI control relinquished.
SPIA has got control of PLL pages
PLL Pages SPI control relinquished.
Sysref Read as expected
SPIA has got control of PLL pages
PLL Pages SPI control relinquished.
Setting RBD to: 28
Setting RBD to: 28
SPIA has got control of PLL pages
PLL Pages SPI control relinquished.
###########Device DAC JESD-RX 0 Link Status###########
lane0 Errors=0b10000; Got errors: elastic buffer overflow (bad RBD value);
lane1 Errors=0b10000; Got errors: elastic buffer overflow (bad RBD value);
lane2 Errors=0b10000; Got errors: elastic buffer overflow (bad RBD value);
lane3 Errors=0b10000; Got errors: elastic buffer overflow (bad RBD value);
CS State TX0: 0b10101010 . It is expected to be 0b10101010
BUF State TX0: 0b11111111 . It is expected to be 0b11111111
Couldn't get the link up for device RX: 0; Alarms: 0x1010101000000000L
###################################
###########Device DAC JESD-RX 1 Link Status###########
lane0 Errors=0b10000; Got errors: elastic buffer overflow (bad RBD value);
lane1 Errors=0b10000; Got errors: elastic buffer overflow (bad RBD value);
lane2 Errors=0b10000; Got errors: elastic buffer overflow (bad RBD value);
lane3 Errors=0b10000; Got errors: elastic buffer overflow (bad RBD value);
CS State TX0: 0b10101010 . It is expected to be 0b10101010
BUF State TX0: 0b11111111 . It is expected to be 0b11111111
Couldn't get the link up for device RX: 1; Alarms: 0x1010101000000000L
###################################
#Done executing .. AFE7950/bringup/script14.py
#End Time 2023-06-26 10:06:20.337000
#Execution Time = 53.3489999771 s
#================ ERRORS:20, WARNINGS:0 ================#
By the way, the FPGA program I have used is also from TI's vcu118_64b66b ip, I change the Pins and the parameter of Transceivers Wizard to adapt the VCU128 and my LMFS/line rates. but the ILA only shows the registers with the input sine signal but no signal on the scope, the ADC also had no response in the ila which are 0000. There are some warnings in the vivado messages log, which is show in the followings:
Synthesis
synth_1
[Constraints 18-1056] Clock 'fpga_ref_clk' completely overrides clock 'sys_clk_p'.
New: create_clock -period 6.400 -name fpga_ref_clk [get_ports sys_clk_p], ["D:/Users/ww/vcu128_6466b/vcu118_64b66b/constraints.xdc": and 2]
Previous: create_clock -period 8.138 [get_ports sys_clk_p], ["d:/Users/ww/vcu128_6466b/vcu118_64b66b/xilinx_ip/sys_pll/sys_pll/sys_pll_in_context.xdc": and 1]
Implementation
Design Initialization
[Constraints 18-1055] Clock 'fpga_ref_clk' completely overrides clock 'sys_clk_p', which is referenced by one or more other constraints. Any constraints that refer to the overridden clock will be ignored.
New: create_clock -period 6.400 -name fpga_ref_clk [get_ports sys_clk_p], ["D:/Users/ww/vcu128_6466b/vcu118_64b66b/constraints.xdc": and 2]
Previous: create_clock -period 8.138 [get_ports sys_clk_p], ["d:/Users/ww/vcu128_6466b/vcu118_64b66b/xilinx_ip/sys_pll/sys_pll.xdc": and 56]
[Designutils 20-1281] Could not find module 'vio_ilas'. The XDC file d:/Users/ww/vcu128_6466b/vcu118_64b66b/xilinx_ip/vio_ilas/vio_ilas.xdc will not be read for this module.
[Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks -of_objects [get_pins TI_IP_inst/mgt_tx_usrclk2]]'. ["D:/Users/ww/vcu128_6466b/vcu118_64b66b/constraints.xdc":10]
[Vivado 12-5201] set_clock_groups: cannot set the clock group when only one non-empty group remains. ["D:/Users/ww/vcu128_6466b/vcu118_64b66b/constraints.xdc":10]
Route Design[Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
It is all about the XDC files, but I only change the pin locations for the vcu128 and AFE7950.
I am very very confused now. Could you please help me find the possible reason? I would much appreciate about that.
