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AFE7950: The bit in the PLL_REG_SPI_A_ACK field does not change to 1.

Park Jungsun
Prodigy 20 points
Part Number: AFE7950
Other Parts Discussed in Thread: LMK04828,

Hello,

My board consists of an MPSoC (XCZU11EG@AMD) + LMK04828 + AFE7950 configuration.

I control AFE7950 using the SPI from the PS (Processing System).

I have configured the AFE7950 registers using a log file generated by the Latte software.

The bit in the PLL_REG_SPI_A_ACK field does not change to 1 during rstDevice/step1.

Since chip_type, chip_id, and chip_ver are read correctly in rstDevice/step0, the SPI is functioning properly.

Rebuilding the FPGA image and changing only the bitstream results in proper AFE7950 configuration and successful JESD Sync.

Subsequently, without any FPGA code modifications, when I rebuild the image and perform tests, the PLL_REG_SPI_A_ACK field's bit not changing to 1 issue occasionally occurs.

What could be the cause of the PLL_REG_SPI_A_ACK field not changing to 1?

Could this phenomenon be dependent on the FPGA image?

Thank you!

Regards,

Park

2023.07.31_mmWave_AFE7950.txt

  • 0
    TI__Genius 17891 points

    Hi Park,

    There are a couple of things that should be checked: 

    1. Is the clock to the AFE stable before programming?
    2. Have you verified all the power rails for the AFE are stable and can provide sufficient current to the AFE? I would suggest probing as close to the device as possible.
    3. How many iterations do you have for each poll? 

    Regards,

    David Chaparro

  • 0 in reply to David Chaparro
    Prodigy 20 points

    Hi David,

    Thank you for your response.

    I have confirmed that the issue was caused by SPI communication problems.

    I resolved the problem by modifying the internal SPI structure of the MPSoC.

    Thank you.

    Regards,

    Park