• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 10 subscribers
  • Views 255 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DAC38RF93: Layout recommendations vs eval card

Dustin Drummond
Prodigy 10 points
Part Number: DAC38RF93

Looking at the layout files for the DAC38RF8xEVM there's a slit in the GRD layers to separate the digital (JESD) from the analog side of the chip. The data sheet for the DAC section 11, Layout Guidelines does not mention needing a slit in the ground plans.  Just wondering if new designs should incorporate this slit into their artwork or if this is not necessary. 

  • 0
    TI__Expert 5645 points

    Dustin,

    Our experience with other EVMs for similar TI devices shows better isolation of noise from the JESD interface onto the RF output when including the cut in the GND plane. The cut is not strictly required but in general, TI recommends following the layout used on the DAC38RF8xEVM. 

    Hope this helps,

    Ben Uhing