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AFE7900EVM: AFE7900EVM integration on custom board developped for project with only FMC connector

Part Number: AFE7900EVM
Other Parts Discussed in Thread: AFE7900, , LMK04828

Hello,

In order to quickly develop my prototype, based on the FPGA and the AFE7900 chip, I would like to integrate the AFE7900EVM evaluation board on my own FPGA platform via an FMC connector.

I've studied the schematics of the AFE7900EVM, all signals, used to control the main functions of the AFE7900, can be used by an external board (via FMC connector). This is only possible if several resistors are mounted or not.

However, the internal clock generator (LMK04828) appears to be configurable only via the USB link (FT4232H) implemented on the AFE7900EVM. It is therefore necessary to use USB to configure the LMK04828 clock generator.
Can you confirm my analysis? Or can you tell me if it's possible to integrate the AFE7900EVM board on a custom FPGA motherboard (via the FMC connector) without USB configuration, only via the FMC connector?

Best regards

B_PINARD

  • Hi Benoit,

    You are correct, the LMK SPI is only routed to the FTDI chip. On all future boards we will be fixing this. 

    For the current boards we have been able to overcome this by blue wiring the LMK SPI. The below changes can be made to AFE EVM to connect LMK SPI to the FMC connector. These changes should be made in addition to the changes for the AFE SPI.

    For the LMK_SCK we connected a wire from R248 to R88.

    For the LMK_SDIO we connected a wire from R249 to R87.

    For the LMK_CS we connected a wire from R242 to the top pad of R9. (To avoid tearing a pad you can also populate R9 with a large resistor, 1MΩ, and connect the wire to this resistor, on the side to connects to the FMC connector)

    Regards,

    David Chaparro

  • Hi David,

    Thank you for your answer. One last question about the function of CPLD.

    CPLD is connected on AFE7900, some of its signals can be disconnected or are GPIO => No problem

    However, the AFE7900 sleep pin is only connected to CPLD without FMC interaction => This is a problem
    1. What are CPLD functions? Is it important to proper functioning ?

    2. Is it possible to customize CPLD VHDL to achieve communication between CPLD-FMC via SPI link (SPIA + FPGA2CPLD like SEN for example)?

    Regards,

    Benoit

  • Hi Benoit,

    1. We do not use the CPLD and on most of the EVMs it will be removed. It will have no role in programming/controlling the AFE with the AFE79xx GUI. If the sleep pin is needed then you may have to blue wire it to a open pin on the FMC connector. 

    2. Since we do not use the CPLD this is something that we have not tested before. We likely do not have any VHDL that can be used as a reference for this. 

    Regards,

    David Chaparro