Other Parts Discussed in Thread: AFE7920
Hi Team,
I recently did an experiment with AFE7920EVM, where at the input of it's ADC A I bring 0 dBm signal @ 600 MHz, and then I measure the signal at the DAC A output.
DAC A NCO frequency is set to 2245 MHz.
Weirdly, I recorded at the output a signal that is slightly higher than what input is providing (0.82 dBm).
To be sure, I also measured input of the ADC A, and with all the cable and connector losses, input signal RF power adds up to -0.1 dBm (i.e., loss of 0.1 dB).
I wanted to know if the DSAs on-board AFE7920 can actually provide in anyway an active gain, or did I somehow miss anything.
If not DSA, could you provide any insight on what could cause more power on output than on input?
Please find attached bellow the code I used for this.
Kind regards,
Željko
Step 0 -> initialization and setup
########## AFE79xx mandatory initialization procedure ##########
# Clear previous sessions:
mainWindow.clearSession()
base_directory = "C:\\Users\\laboadmin\\Documents\\Texas Instruments\\Afe79xxLatte\\projects\\AFE79xx\\digitalBoardVLBI_flex\\"
# Initialize AFE board:
mainWindow.runFile(base_directory + r"setup.py")
mainWindow.runFile(base_directory + r"devInit.py")
# Perform device reset:
AFE.deviceSoftReset()
info('')
info('************************************************************')
info(' Mandatory AFE initialization complete')
info('************************************************************')
info('')
Step 1 -> parameter selection
########## General settings: ##########
# VLBI Tx frequency plan details:
custom_clk = 3 # Pick AFE frequency plan scenario.
enableAnalogRepeater = True # Enable/disable AFE in analog loopback configuration (DACs transmitting from ADCs).
dualLanePerSignal = False # Pick 2 lanes (True) or 4 lanes (False) to transmit signal via JESD lines.
enableAdcDacSync = True # Enable sync signal between ADCs and DACs and FPGA by disabling LVDS sync that fixes GPIO pins.
ADCenable = { "A": 1, # Select which ADCs are enabled during AFE operation.
"B": 1,
"C": 1,
"D": 1}
enableTxRxScrambling = True
setTxRxFbK = 16
separateLinks = False
jesdSystemMode = [3, 3]
enableMux = {'Tx': False, 'Rx': False}
useSpiSysref = True # Enable (when debugging)/disable (in real operation) internal SYSREF signal.
Fnco_tx1 = 2245.0
Fnco_tx4 = 6812.5
ncoFreqModes = ["1KHz", "FCW"]
syncLoopBack = bool(1-enableAnalogRepeater)
jesdLoopbackEn = bool(enableAnalogRepeater)
enableLVDSsync = bool(1-enableAdcDacSync)
fbJesdTxSyncMux = 3 if enableLVDSsync else 1
gpioMapping = { 'H8': 'ADC_SYNC0',
'H7': 'DAC_SYNC0',
'N8': 'ADC_SYNC2',
'N7': 'ADC_SYNC3',
'H9': 'ADC_SYNC1',
'G9': 'DAC_SYNC1',
'N9': 'DAC_SYNC2',
'P9': 'DAC_SYNC3',
'P14': 'GLOBAL_PDN',
'K14': 'FBABTDD',
'R6': 'FBCDTDD',
'H15': ['TXATDD','TXBTDD'],
'V5': ['TXCTDD','TXDTDD'],
'E7': ['RXATDD','RXBTDD'],
'R15': ['RXCTDD','RXDTDD']}
if custom_clk == 0:
# TI template configuration at TI clock reference
f0 = 122.88
Nrx = 24
Nddc = 6
Ntx = 4
NFRef = 4
NfpgaRefClk = 1#2
NinputClk = 8#12
LMFSHdTx = ['44210', '44210', '44210', '44210']
warning("TI reference design selected! Make sure FPGA and clock reference are properly set up")
elif custom_clk == 3:
# Forked VLBI setup
f0 = 122.76
Nrx = 24
Nddc = 6
Ntx = 4
NFRef = 1
NfpgaRefClk = 1
NinputClk = 1
Nlanes = '2' if dualLanePerSignal else '4'
Nconv = Nlanes
LMFSHdTx = [Nlanes+Nconv+'210']*4
if custom_clk != 0: warning("Custom configuration selected! Make sure FPGA and external clock reference are properly connected and set up")
LMFSHdRx = LMFSHdTx
LMFSHdFb = ['22210', '22210']
Nduc = Nddc*Ntx
info('Tx & Rx LMFSHd settings: '+LMFSHdTx[0])
info('')
info('------------------------------------------------------------')
info('User configuration:')
if enableAnalogRepeater:
info(' Analog repeater')
else:
info(' Digital repeater')
if enableAdcDacSync:
info(' LVDS sync disabled - ADC and DAC sync enabled')
else:
info(' LVDS sync enabled - ADC and DAC sync disabled')
if custom_clk:
info(' External clock reference used: '+str(f0)+'MHz')
else:
info(' Internal AFE clock reference used: '+str(f0)+'MHz')
info('------------------------------------------------------------')
info('')
info('************************************************************')
info(' User parametrization complete')
info('************************************************************')
info('')
Step 2 -> AFE setup
########## AFE79xx analog front-end setup ##########
# AFE general settings
AFE.systemStatus.loadTrims = 1
setupParams.skipFpga = 1
setupParams.fpgaRefClk = f0*NfpgaRefClk
sysParams = AFE.systemParams
sysParams.__init__()
sysParams.chipVersion = chipVersion
sysParams.FRef = f0*NFRef
##sysParams.executeLinkUpSequenceSeparately = separateLinks
########## Analog settings: AFE 79XX EVM ##########
# General system settings
sysParams.RRFMode = 0
sysParams.modeTdd = 0
##sysParams.adcSelect0 = [0, 1, 2]
##sysParams.adcSelect1 = [0, 1, 2]
sysParams.useSpiSysref = useSpiSysref
##sysParams.sysrefTermination = 0
sysParams.ncoFreqMode = ncoFreqModes[custom_clk != 0]
sysParams.spiMode = 1
# ADC settings
sysParams.FadcRx = f0*Nrx
info('ADC sampling rate: '+str(sysParams.FadcRx)+'MHz')
sysParams.rxEnable = [ ADCenable["A"],
ADCenable["B"],
ADCenable["C"],
ADCenable["D"]]
sysParams.externalClockRx = 0
##sysParams.halfRateModeRx = [0, 0]
sysParams.ddcFactorRx = [Nddc]*4
info('ADC down-conversion factors: '+str(sysParams.ddcFactorRx))
sysParams.numBandsRx = [0]*4
##sysParams.numRxNCO = 1
##sysParams.ncoRxMode = [0, 0]
##sysParams.broadcastRxNcoSel = 0
sysParams.rxNco0 = [[600.0]*2,
[600.0]*2,
[600.0]*2,
[600.0]*2]
info('ADC NCOs: '+str(sysParams.rxNco0[0][0])+'MHz, '+str(sysParams.rxNco0[1][0])+'MHz, '+str(sysParams.rxNco0[2][0])+'MHz, '+str(sysParams.rxNco0[3][0])+'MHz')
# FB settings
sysParams.FadcFb = sysParams.FadcRx
info('FB ADC sampling rate: '+str(sysParams.FadcFb)+'MHz')
sysParams.fbEnable = [0, 0]
##sysParams.halfRateModeFb = [0, 0]
sysParams.ddcFactorFb = [Nddc]*2
info('FB ADC down-conversion factors: '+str(sysParams.ddcFactorFb))
sysParams.numBandsFb = [0, 0]
##sysParams.numFbNCO = 1
##sysParams.ncoFbMode = 0
sysParams.fbNco0 = [1000, 1000]
sysParams.fbNco1 = [1000, 1000]
sysParams.fbNco2 = [1000, 1000]
sysParams.fbNco3 = [1000, 1000]
info('FB ADC NCOs: '+str(sysParams.fbNco0[0])+'MHz, '+str(sysParams.fbNco1[0])+'MHz')
# DAC settings
# AFE7920 DAC sampling rate must fall into one of the following frequency ranges (due to pll restrictions): [7.2 GHz, 7.68 GHz] or [8.8 GHz, 9.1 GHz] or [9.7 GHz, 10.24 GHz] or [11.6 GHz, 12.08 GHz]
sysParams.Fdac = sysParams.FadcRx*Ntx
info('DAC sampling rate: '+str(sysParams.Fdac)+'MHz')
sysParams.txEnable = [1, 1, 1, 1]
sysParams.externalClockTx = 0
##sysParams.halfRateModeTx = [0, 0]
sysParams.ducFactorTx = [Nduc]*4
info('DAC up-conversion factors: '+str(sysParams.ducFactorTx))
sysParams.numBandsTx = [0, 0, 0, 0]
##sysParams.numTxNCO = 1
##sysParams.combineDucMode = [0, 0]
sysParams.enableDacInterleavedMode = 0
##sysParams.ncoTxMode = [0, 0]
##sysParams.broadcastTxNcoSel = 0
sysParams.txNco0 = [[Fnco_tx1]*2,
[5020.0]*2,
[8212.5]*2,
[Fnco_tx4]*2]
info('DAC NCOs: '+str(sysParams.txNco0[0][0])+'MHz, '+str(sysParams.txNco0[1][0])+'MHz, '+str(sysParams.txNco0[2][0])+'MHz, '+str(sysParams.txNco0[3][0])+'MHz')
info('')
info('************************************************************')
info(' Analog front end setup complete')
info('************************************************************')
info('')
Step 3 -> JESD setup
########## AFE79xx EVM JESD204b settings ##########
sysParams.topLevelSystemMode = 'StaticTDDMode'
sysParams.jesdSystemMode = jesdSystemMode
sysParams.serdesFirmware = 1
sysParams.jesdABLvdsSync = enableLVDSsync
sysParams.jesdCDLvdsSync = enableLVDSsync
sysParams.syncLoopBack = syncLoopBack
sysParams.jesdLoopbackEn = jesdLoopbackEn
sysParams.LMFSHdRx = LMFSHdRx
sysParams.jesdRxProtocol = [0]*2
sysParams.jesdRxLaneMux = [0, 1, 2, 3, 4, 5, 6, 7]
sysParams.jesdRxRbd = [4]*2
sysParams.rxJesdTxScr = [enableTxRxScrambling]*4
sysParams.rxJesdTxK = [setTxRxFbK]*4
##sysParams.rxJesdTxSyncMux = [0]*4
##sysParams.rxDataMux = [0, 1, 2, 3, 4, 5, 6, 7]
##sysParams.serdesRxLanePolarity = [0]*8
##sysParams.adcDataMuxEn = enableMux['Tx']
sysParams.LMFSHdFb = LMFSHdFb
sysParams.fbJesdTxScr = [enableTxRxScrambling]*2
sysParams.fbJesdTxK = [setTxRxFbK]*2
##sysParams.fbJesdTxSyncMux = [fbJesdTxSyncMux, fbJesdTxSyncMux]
##sysParams.fbDataMux = [0, 1]
sysParams.LMFSHdTx = LMFSHdTx
sysParams.jesdTxProtocol = [0]*2
sysParams.jesdTxLaneMux = [0, 1, 2, 3, 4, 5, 6, 7]
#sysParams.jesdTxRbd = [4, 4]
sysParams.jesdRxScr = [enableTxRxScrambling]*4
sysParams.jesdRxK = [setTxRxFbK]*4
##sysParams.jesdRxSyncMux = [0]*4
##sysParams.txDataMux = [0, 1, 2, 3, 4, 5, 6, 7]
##sysParams.serdesTxLanePolarity = [0]*8
##sysParams.dacDataMuxEn = enableMux['Rx']
#sysParams.serdesTxPreCursor = [6, 6, 6, 6, 6, 6, 6, 6]
#sysParams.serdesTxPostCursor = [0, 0, 0, 0, 0, 0, 0, 0]
#sysParams.serdesTxMainCursor = [3, 0, 0, 0, 0, 0, 0, 3]
##sysParams.setIlaParams = 1
##sysParams.jesdTxIlaM = [8, 8, 2, 8, 8, 2]
##sysParams.jesdTxIlaLid = [0, 1, 2, 3, 4, 5, 6, 7]
##sysParams.jesdTxIlaL = [4, 4, 2, 4, 4, 2]
########## Remap AFE pins to adjust for the FW/FPGA design ##########
sysParams.gpioMapping = gpioMapping
info('')
info('************************************************************')
info(' JESD setup complete')
info('************************************************************')
info('')
Step 4 -> LMK setup
########## Clock distribution mode and LMK setup ##########
lmkParams.pllEn = (custom_clk == 0)
lmkParams.inputClk = f0*NinputClk
lmkParams.lmkFrefClk = True
lmkParams.lmkPulseSysrefMode = False
lmk.rawWriteLogEn = 1
lmk.logEn = 1
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat = 0x01
logDumpInst.rewriteFile = 1
logDumpInst.rewriteFileFormat4 = 1
device.optimizeWrites = 0
device.rawWriteLogEn = 1
device.delay_time = 0
setupParams.skipLmk = False
AFE.initializeConfig()
lmkParams.sysrefFreq = AFE.systemStatus.sysrefFreq
AFE.LMK.lmkConfig()
# Force Latte to program the LMK outputs (relevant to the FPGA) in bypass/distribution mode when external reference clock is applied:
if custom_clk != 0:
lmk.head.page.DCLK0_SDCLK1_controls.Analog_Dig_Delay.dclk_mux_lt_1_0_gt_ = 2
lmk.head.page.DCLK8_SDCLK9_controls.Analog_Dig_Delay.dclk_mux_lt_1_0_gt_ = 2
lmk.head.page.DCLK8_SDCLK9_controls.Analog_Dig_Delay.sdclk_mux = 1
lmk.head.page.DCLK12_SDCLK13_controls.Analog_Dig_Delay.dclk_mux_lt_1_0_gt_ = 2
setupParams.skipLmk = True
info('')
info('************************************************************')
info(' LMK setup complete')
info('************************************************************')
info('')
Step 5 -> AFE7920 bringup
########## AFE79xx device bring-up ##########
AFE.deviceBringup()
AFE.TOP.overrideTdd(15, 3, 15)
#AFE.TOP.overrideTdd(15, 0, 15)
info('')
info('************************************************************')
info(' AFE bringup complete')
info('************************************************************')
info('')
