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AFE7900: AFE7900 TI-204B/C Interface

Muhammad Umer
Prodigy 120 points
Part Number: AFE7900


Hi, 

I am using AFE7900. I need TI-JESD204B/C IP for the following board (Avnet UltraZed-7EV SOM (xczu7ev-fbvb900-1-i)). 

Can TI-204C IP supports this development board?

I also need some clarity about the parameters of AFE7900 for the following configurations

  • ADC Sampling rate = 2949.12MSPS
  • Decimation Rate    = 24
  • Interface Rate    =  2949.12/24 = 122.88MSPS ?
  • L-M-F-S-HD     =   1  - 2 - 4 - 1 - 0 ( These parameters indicates that each JESD RX link (RX A or RX B) 

For my understanding RXA samples are coming in single lane (L). Converter(M) 2 corresponds to one I Sample and one Q sample. F(Octet per frame) indicates 4 octet in one lane. 

Can my understanding is correct?

  • Serdes Rate    =   4.9152Gbps
  • System Reference Clock  =  1.92Mhz ( sysref)    is it frequency is correct? 

The above settings explain the Interface rate at the output of DDC is 122.88MSPS. Can my understanding is correct ?

What will be  reference clock for the serdes in JESD204B interface

6)  Reference Clock   = 122.88 or 245.76?

We are using jesd system mode 0 for our testing. Please  clarify that my understanding is correct? 

 

  • 0
    TI__Genius 10895 points

    Hi Muhammad,

    Muhammad Umer said:

    I am using AFE7900. I need TI-JESD204B/C IP for the following board (Avnet UltraZed-7EV SOM (xczu7ev-fbvb900-1-i)). 

    Can TI-204C IP supports this development board?

    The TI JESD-204C IP supports this board (Zynq UltraScale+ FPGA). All supported Xilinx FPGA families are given in the IP webpage: https://www.ti.com/tool/TI-JESD204-IP

    You can request for the IP in the same webpage.

    Muhammad Umer said:
    • ADC Sampling rate = 2949.12MSPS
    • Decimation Rate    = 24
    • Interface Rate    =  2949.12/24 = 122.88MSPS ?
    • L-M-F-S-HD     =   1  - 2 - 4 - 1 - 0 ( These parameters indicates that each JESD RX link (RX A or RX B) 

    For my understanding RXA samples are coming in single lane (L). Converter(M) 2 corresponds to one I Sample and one Q sample. F(Octet per frame) indicates 4 octet in one lane. 

    Can my understanding is correct?

    Yes. This is correct. For one RX channel, LMFS is 12410. For 4 channels, L and M parameters would be four times i.e. LMFS:48410.

    Muhammad Umer said:

    Can my understanding is correct?

    • Serdes Rate    =   4.9152Gbps
    • System Reference Clock  =  1.92Mhz ( sysref)    is it frequency is correct? 

    SERDES rate is correct. SYSREF frequency depends on DAC sample rate and interpolation factor also. But 1.92MHz works for ADC rates you described. When AFE configuration script is run in AFE79xx EVM software, SYSREF frequency that should be used is shown in the log window. 

    Muhammad Umer said:
    The above settings explain the Interface rate at the output of DDC is 122.88MSPS. Can my understanding is correct ?

    Yes. Correct

    Muhammad Umer said:

    What will be  reference clock for the serdes in JESD204B interface

    6)  Reference Clock   = 122.88 or 245.76?

    When using TI-JESD204 IP, FPGA  reference clock will SERDES lane rate divided by 80 i.e. 61.44MHz for 4915.2Gbps lane rate. 

    Muhammad Umer said:
    We are using jesd system mode 0 for our testing. Please  clarify that my understanding is correct? 

    If you plan to use all 4 channels, you can use JESD system mode 1.

    Below RX ADC JESD configuration can be used:

    		#####	ADC-JESD	#####
sysParams.jesdSystemMode= [1,1]
													#SystemMode 0:	2R1F-FDD						; rx1-rx2-fb -fb
													#SystemMode 1:	1R1F-FDD						; rx -rx -fb -fb
													#SystemMode 2:	2R-FDD							; rx1-rx1-rx2-rx2
													#SystemMode 3:	1R								; rx -rx -rx -rx
													#SystemMode 4:	1F								; fb -fb- fb -fb
													#SystemMode 5:	1R1F-TDD						; rx/fb-rx/fb-rx/fb-rx/fb
													
sysParams.jesdTxProtocol= [0,0]						# 0 - 8b/10b encoding; 2 - 64b/66b encoding 
sysParams.LMFSHdRx		= ["24410","24410","24410","24410"]

    Regards,

    Vijay

  • 0 in reply to Vijayendra Varma Siddamsetty
    Prodigy 120 points

    Hi Vajay,

    Thanks for your detailed reply for the above questions.

    One thing that I didn't get why the reference clock is 61.44Mhz for the 4.9152Gbps serdes rate? 

    L-M-F-S-Hd   is  1 - 2 - 4 - 1 - 0

    The Octet per frame (F) is set to 4 in the above settings. This indicates that in one lane we get 32 bits (4 Octets) per lane. One I sample(16 bits) and one Q sample (16bits). Should the reference clock will be (SERDES RATE/40) ? i-e 122.88 Mhz?

    Please correct me if the above understanding is wrong

    Thanks

    Regards

    Muhammad Umer  

  • 0 in reply to Muhammad Umer
    TI__Genius 10895 points

    Hi Muhammad,

    Sorry for the delay.

    Your calculation is correct. The output sample rate is 122.88MSPS. But this need not be equal to FPGA refence clock. In TI JESD204 IP, SERDES lane output data is parallelized to 80 streams. That's why reference clock will be equal to 61.44MHz. Two data samples will be outputted on each clock cycle. 

    Regards,

    Vijay