AFE7769DEVM: Serdes lane swap

Hi Alder,

Please advise your definition for lane swap. Do you mean the positive and negative leg of the SerDes are in reverse with respect to the FMC VITA57 specification? If so, we may have done so in order to optimize the layout of the AFE7769D EVM to preserve the best signal integrity.

For the AFE7769D, we do have the option to programmable reverse the polarity of the P/N leg of the SRX/STX ports of the AFE7769D SerDes block.

-Kang

Referring to AFE7769D EVM , J21A FMC connector.

Pin A2, A3 suppose the FMC standard connection is for DP1, however, the EVM is connected to DP0 (DP0_FMC_P/N)

was the swapped set in the AFE7769D device by CPLD?

Let say, if i am designing a FPGA FMC mating connector to AFE7769DEVM, i just want to double confirm that i do not need the serdes DP lanes swapping on my side, was that true?

Hi Alder,

Yes, agreed the original VITA57 spec calls the A2 and A3 to be DP1_M2C_P and DP1_M2C_N, respectively. However, TI's AFE7769D in the EVM design simply route 2STX+/- lanes to such ports to A2 and A3. Therefore, as long as you make sure that your JESD204 receiver on A2 and A3 are looking for lane data from STX2+/-, the data and handshake should happen as expected.

This is not a lane swap. Rather, this is a simple definition/nomenclature change. No, the CPLD does not control any of this.

The AFE7769D (with DPD) is different than the AFE7769 (non-DPD version). The AFE7769D only has four STX lanes (STX1 to STX4) and four SRX lanes (SRX1 to SRX4). 

When I mention about internal lane swap, what I meant is that STX2 usually carries RF uplink channel 2 data (while STX1 usually carries RF uplink channel 1 data), as an example. However, if today if you want STX2 to carry RF uplink channel 1 data, we have an internal muxing feature to mux the RF data around to fit into different STX lanes (i.e. JESD204 lanes). Hope this helps.