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Original question:

AFE7950EVM: About AFE7950 JESD204B lanes

AFE7950EVM: AFE7950: AFE7950 TI-JESD204B IP & LANES

xiao zhang
Prodigy 70 points
Part Number: AFE7950EVM

Hi, 

I am using AFE7950EVM. I need TI-JESD204B IP for the following board (Xilinx ZCU102 (xczu9eg-ffvb1156-2-e)). 

  1. I request the TI-204B IP from web, and reply the parametar form by email(use case CS1996701) , but I never found the free TI-204B IP in the secure resource. so, I request the IP application again via web, the case num is CS2022950.  How can I get this free JESD204 IP as soon as possible?

  2. meanwhile, I use Xilinx JESD204 interface to send or receive data. Do you provide UI tools for debugging the JESD204 inrerface? On the AFE side, I use the "TI_IP_10Gbps_8Lane_ConfigLmk.py",and the configuration is as follows:       

  • sysParams.fbEnable = [False]*2        
  • sysParams.LMFSHdTx   44210   and  sysParams.LMFSHdTx   44210
  • sysParams.FadcFb = 2949.12
  • sysParams.Fdac = 2949.12*4
  • sysParams.ddcFactorRx = [6]*4 
  • sysParams.ducFactorTx = [24]*4
  • K =32 

therefore, 

serdes rate = 9.8304Gbps

  • ADC Sampling rate = 2949.12MSPS
  • Decimation Rate    = 6
  • Interface Rate    =  2949.12/6 = 491.52MSPS 
  • L-M-F-S-HD     =   4-4-2-1 -0 
  • DAC Sampling rate = 2949.12MSPS *4 = 9830.4MSPS 
  • Decimation Rate    = 24
  • Interface Rate    =  2949.12*4/24 = 491.52MSPS 
  • L-M-F-S-HD     =   4-4-2-1-0 

If i use Xilinx JESD204 IP, should I choose one 8-lanes JESD or two 4-lanes IP ?

I confige parameter as follows，can my understanding is correct ?

  • L-M-F-S-HD  = 8-8-2-1-0 ?
  • sysclk(glbclk) = serdes rate/40 = 245.76MHz ?
  • refclk = 122.88MHz ?
  • sysref = 3.84MHz ?
  • 0
    TI__Genius 14961 points

    Hi Xiao,

    Access to the TI-204c IP was granted and you should be receiving an email with the link to follow. 

    The reference design that is available in the secure folder uses the mode you mention above, so once you can access the TI204c-IP you can use this project. 

    When using the Xilinx JESD204 IP you should choose one 8-lane IP. LMFS is 88210, sysclk is 245.76MHz, and sysref is 3.84MHz. The Fref to the AFE should not be changed and should be 491.52MHz. 

    Regards,

    David Chaparro 

  • 0 in reply to David Chaparro
    Prodigy 70 points

    Hi David，

    thanks for your reply!

    1. I didn't changes on the AFE side and the Fref = 491.52MHz;

       using the Xilinx JESD204 IP, I choose one 8-lane IP. LMFS is 88210, sysclk is 245.76MHz;

       I choose the refclk is 122.88MHz(from 7950EVM) for FPGA GTH. Is this configuration correct ? ? ?

    2. Due to the physical layer of Xilinx JESD204 IP  is 32bit;  if I choose LMFS is 8821,the data bit of tx_tdata is 32*8=256bit; 

    LANE_DAC_TO_GT_MAP {4,5,6,7,3,0,2,1}  ( from jesd_link_params.vh)

    AFE channel AFE DAC lane number FPGA TX IP lane number Signal data
    TxA_I 0 1 {AI1,AI0},{AI3,AI2},...
    TxA_Q 1 2 {Bq1,Bq0},{Bq3,Bq2},...
    TxB_I 2 0 {AI1,AI0},{AI3,AI2},...
    TxB_Q 3 3 {Bq1,Bq0},{Bq3,Bq2},...
    TxC_I 4 7 {Dq1,Dq0},{Dq3,Dq2},...
    TxC_Q 5 6 {DI1,DI0},{DI3,DI2},...
    TxD_I 6 5 {Cq1,Cq0},{Cq3,Cq2},...
    TxD_Q 7 4 {CI1,CI0},{CI3,CI2},...

    there,the I1,q1,... is 16bit (a frame/ sample data bit)

    So, the tx_tdata is concatenated into {{CI1,CI0},{CI3,CI2},  {Cq1,Cq0},{Cq3,Cq2},    {DI1,DI0},{DI3,DI2}, {Dq1,Dq0},{Dq3,Dq2},    {Bq1,Bq0},{Bq3,Bq2}, {AI1,AI0},{AI3,AI2},   {Bq1,Bq0},{Bq3,Bq2}, {AI1,AI0},{AI3,AI2}},  and total 256bit for Xilinx JESD204 IP.

    Is this data physical mapper relation correct ? ? ?

    and whether the I/Q data of TxA is tranfrom by lane0/lane1 ? ? ？

  • 0 in reply to xiao zhang
    TI__Genius 14961 points

    Hi Xiao,

    The ref clock should be set to frequency that you choose in the transceiver wizard. When using the TI IP we choose the ref clock frequency to be the same as the sysclk. 

    The data physical mapper relation that you show looks to be correct, but  I cannot be too sure as I am not familiar with the Xilinx JESD204 IP. 

    I see that you have access to our TI 204c IP. Have you had a chance to look at this? We have reference designs available for the mode you are looking at.

    Regards,

    David Chaparro