Hello,
Our customer used DAC38RF82 for his application, when configuring DAC38RF82 81180 mode, 8G sample rate can be output, but 9G cannot output.
DAC38RF82 81180 9G mode does not output. Using internal PLL, input clock 281.25MHz, N=1, M=8, VCO=9000MHz
DAC38RF82 81180 8G mode but normal output, internal PLL, input clock 250MHz, N=1, M=8, VCO=8000MHz
And he did some test:
He found that the DAC internal phase-locked ring did have a problem with 9G sample rate and then confirm that the reference clock of the external input is stable and the error is reasonable. Since 8G sample rate can be played properly, the input power should be fine.
The related several registers are configured as follows:
0x31: 0x0400
0x32: 0x0708
0x33: 0x8A14
Because the 8G sample rate plays well, a lock exception occurs when the DAC clock is changed to the 9G sample rate for this input only.
He also read the JESD_ALM registers (addrss:0x64~0x6B),he read 0xA, does it affect the DAC output?
PS:JESD Alarms for Lane 0~7 Register[3:0] ,ALM_FIFO0_FLAGS Field。
Best regards
kailyn