AFE7769DEVM: Length matching clarification when mating with AFE7769DEVM

Hi Alder,

Alder Lim said:

1. Is TI ask to matching length for both clock (FTXCLK_P/N & FPGA_SYSREF_P/N) on the mating board as well ? 

No, this is not a strict requirement. The JESD204 standard only specify the clocking on the JESD204 side to be deterministic. This means when the clocking device (i.e. the LMK04828 on the AFE7769D EVM) will need to output the clock and SYSREF with the same aligned phase information upon every reset and power-up. As long as the clock and SYSREF traces are routed to ensure to meet the specified AFE7769D SYSEF to clock setup/hold time, and also can ensure deterministic phase upon power-up/reset, your design will meet the JESD204 interop.

Alder Lim said:

2. How about CLK_LA0 ? Do i need to match together with FTXCLK_P/N & FPGA_SYSREF_P/N ?

2. CLK_LA0 is another reference clock to another type of FPGA's DLL/PLL circuit. It has the same guidance as earlier.

Alder Lim said:

3. What is the intrapair and interpair spec that TI recommends? (mils/ps) 

3. We have a series of videos to help you up to speed. I can send you the AFE7769D EVM layout with all the DRC limits for you to refer to. 

https://www.ti.com/video/4887179668001?keyMatch=JESD204B

https://www.ti.com/video/4870259786001?keyMatch=JESD204B

https://www.ti.com/video/4870305881001?keyMatch=JESD204B

Alder Lim said:

Also, would you point me to get AFE7769D full datasheet ?

Please sign up for a TI.com login. I will go ahead and grant you access to our internal secure server with datasheet and EVM layout. Thank you!

-Kang