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Original question:

AFE7950EVM: About AFE7950 JESD204B Loopback

AFE7950: “SerDes AB PLL Loss of Lock” Alarm

Yake Li
Prodigy 120 points
Part Number: AFE7950


Hi Team，

      Since you did not answer my previous question, I have created a new one.  I am still working on JESD loopback for AFE7950 chips.

      I used a custom board. So I can only control through SPI and cannot use LATTE.

      I first configure the parameters on Latte, and then export the bring up program log file, which directly controls the registers of AFE. 

      Before executing the bring up program, I have configured the LMK chip and ensured that the clock provided to AFE is correct.

      I noticed that AFE's bring up program also checks for PLL and Sysref, and the program did not report any errors.

      I have tried changing the clock of LMK to a different frequency, and the bring up program of AFE will prompt for an error.

This is the log information of my bring up program during runtime. There were no errors in previous runs, only when an error was reported in 'Reading the JESD RX states to check if link is established'.

//START: Doing AFE Config
//STEP: rstDevice/step0 
//START: Device Soft Reset and SPI Check
//END: Device Soft Reset and SPI Check
//STEP: rstDevice/step1 
//START: Waking up device
//START: Setting TDD Pin in override state and setting override values.
//END: Setting TDD Pin in override state and setting override values.
//END: Done waking up device
//START: Setting MCU Clock Div
//END: Setting MCU Clock Div
//START: Changing termination to 100 ohm
//START: Requesting/releasing SPI Access to PLL Pages
//END: Requesting/releasing SPI Access to PLL Pages
//START: Requesting/releasing SPI Access to PLL Pages
//END: Requesting/releasing SPI Access to PLL Pages
//END: Changing termination to 100 ohm
//STEP: efuseChain/step0 
//START: Loading Efuse Chain
//END: Loading Efuse Chain
//START: Checking for Efuse
//END: Checking for Efuse
//START: enabling Efuse Clock
//END: enabling Efuse Clock
//STEP: mcuWakeUp/step0 
//STEP: mcuWakeUp/step1 
//STEP: pllEfuse/step0 
//START: Enabling Temp Sense
//END: Enabling Temp Sense
//START: Loading PLL EFuse trims
//END: Done Loading PLL EFuse trims
//STEP: pllConfig/step0 
//START: Configuring PLL
//START: Requesting/releasing SPI Access to PLL Pages
//END: Requesting/releasing SPI Access to PLL Pages
//START: Sending Sysref to device
//END: Sending Sysref to device
//START: Requesting/releasing SPI Access to PLL Pages
//END: Requesting/releasing SPI Access to PLL Pages
//END: Configuring PLL
//STEP: pllConfig/step1 
//STEP: serdesConfig/step0 
//START: Enabling access to SERDES
//END: Done enabling access to SERDES
//START: Setting Serdes Reference Clock Divs
//END: Setting Serdes Reference Clock Divs
//STEP: serdesConfig/step1 
//START: Resetting Serdes
//END: Done resetting Serdes
//START: Resetting Serdes
//END: Done resetting Serdes
//STEP: serdesConfig/step2 
//START: Configuring the SERDES
//END: Done configuring the SERDES
//STEP: serdesConfig/step3 
//START: Loading Serdes Firmware.
//END: Done loading Serdes Firmware.
//STEP: topConfig/step0 
//START: Setting Top Control Modes
//END: Setting Top Control Modes
//STEP: topConfig/step1 
//STEP: topConfig/step2 
//STEP: sysConfig/step0 
//START: Configuring RRF Mode to TOP MCU
//END: Configuring RRF Mode to TOP MCU
//STEP: sysConfig/step1 
//START: Configuring RX Chain Parameters to TOP MCU
//END: Configuring RX Chain Parameters to TOP MCU
//STEP: sysConfig/step2 
//START: Configuring FB Chain Parameters to TOP MCU
//END: Configuring FB Chain Parameters to TOP MCU
//STEP: sysConfig/step3 
//START: Configuring TX Chain Parameters to TOP MCU
//END: Configuring TX Chain Parameters to TOP MCU
//STEP: configTune/step0 
//START: Configuring Digital Chain
//END: Configuring Digital Chain
//STEP: configTune/step1 
//START: Setting FIFO Pointers
//END: Setting FIFO Pointers
//STEP: analogWrites/step0 
//STEP: analogWrites/step1 
//START: Removing TDD Pin Overrides.
//END: Removing TDD Pin Overrides.
//START: DAC Analog Writes
//START: Requesting/releasing SPI Access to PLL Pages
//END: Requesting/releasing SPI Access to PLL Pages
//START: Requesting/releasing SPI Access to PLL Pages
//END: Requesting/releasing SPI Access to PLL Pages
//END: DAC Analog Writes
//START: Configuring AUX ADC
//END: Configuring AUX ADC
//STEP: analogWrites/step2 
//START: Removing TDD Pin Overrides.
//END: Removing TDD Pin Overrides.
//STEP: analogWrites/step3 
//START: PLL Ana Trims
//START: Requesting/releasing SPI Access to PLL Pages
//END: Requesting/releasing SPI Access to PLL Pages
//START: Requesting/releasing SPI Access to PLL Pages
//END: Requesting/releasing SPI Access to PLL Pages
//END: PLL Ana Trims
//STEP: jesdConfig/step0 
//START: Configuring JESD Muxes and Pointers
//START: Configuring JESD TX Lane Mux
//END: Configuring JESD TX Lane Mux
//START: Configuring JESD RX Lane Mux
//END: Configuring JESD RX Lane Mux
//START: Configuring the DDC-JESD Data Muxes
//END: Configuring the DDC-JESD Data Muxes
//START: Configuring the JESD-DUC Data Muxes
//END: Configuring the JESD-DUC Data Muxes
//START: Configuring JESD TX Sync Mux
//END: Configuring JESD TX Sync Mux
//START: Configuring JESD RX Sync Mux
//END: Configuring JESD RX Sync Mux
//END: Configuring JESD Muxes and Pointers
//START: Setting JESD SyncB Pin Mode
//END: Setting JESD SyncB Pin Mode
//STEP: jesdConfig/step1 
//START: Configuring ADC JESD TX
//END: Done Configuring ADC JESD TX
//START: Configuring ADC JESD TX
//END: Done Configuring ADC JESD TX
//STEP: jesdConfig/step2 
//START: Configuring DAC JESD RX
//END: Done Configuring DAC JESD RX
//START: Configuring DAC JESD RX
//END: Done Configuring DAC JESD RX
//STEP: jesdConfig/step3 
//STEP: agcConfig/step0 
//STEP: miscConfig/step0 
//START: Configuring Interrupt Pins
//END: Done configuring Interrupt Pins
//START: Power Saving Options
//END: Power Saving Options
//STEP: miscConfig/step1 
//STEP: gpioConfig/step0 
//STEP: sysrefJesdLinkup/step0 
//STEP: sysrefJesdLinkup/step1 
//START: Clearing Sysref Flags
//END: Done clearing Sysref Flags
//STEP: sysrefJesdLinkup/step2 
//START: Sending Sysref to device
//START: Requesting/releasing SPI Access to PLL Pages
//END: Requesting/releasing SPI Access to PLL Pages
//START: Requesting/releasing SPI Access to PLL Pages
//END: Requesting/releasing SPI Access to PLL Pages
//END: Sending Sysref to device
//STEP: sysrefJesdLinkup/step3 
//START: Checking Sysref Flags
//END: Done checking Sysref Flags
//STEP: sysrefJesdLinkup/step4 
//STEP: sysrefJesdLinkup/step5 
//START: Toggling JESD TX Sync override
//END: Toggling JESD TX Sync override
//STEP: postLinkUp/step0 
//START: Writing Post Link up SERDES writes
//END: Done writing Post Link up SERDES writes
//STEP: postLinkUp/step1 
//START: Removing TDD Pin Overrides.
//END: Removing TDD Pin Overrides.
//START: Removing TDD Pin Overrides.
//END: Removing TDD Pin Overrides.
//START: Removing TDD Pin Overrides.
//END: Removing TDD Pin Overrides.
//START: Removing TDD Pin Overrides.
//END: Removing TDD Pin Overrides.
//START: Removing TDD Pin Overrides.
//END: Removing TDD Pin Overrides.
//START: Removing TDD Pin Overrides.
//END: Removing TDD Pin Overrides.
//STEP: postLinkUp/step2 
//STEP: dlJesdLinkupCheck/step0 
//START: Reading the JESD RX states to check if link is established

AFE ID: 0[../src/CAFE2p1/Afe79xx/Src/tiAfe79_basicFunctions.c][ti_afe79_afeSpiCheckWrapper][559]ERROR:addr[0x0119], lsb[0], msb[7], data[0xF0] not matching with expected value[0x00]

AFE ID: 0[../src/app/bringup.c][AFE_Bringup][17558]ERROR:AFE FROM FILE Read Check Fail: 0x0119[0:7] = 0x0000

AFE ID: 0[../src/CAFE2p1/Afe79xx/Src/tiAfe79_basicFunctions.c][ti_afe79_afeSpiCheckWrapper][559]ERROR:addr[0x0118], lsb[0], msb[7], data[0x40] not matching with expected value[0x00]

AFE ID: 0[../src/app/bringup.c][AFE_Bringup][17564]ERROR:AFE FROM FILE Read Check Fail: 0x0118[0:7] = 0x0000

AFE ID: 0[../src/CAFE2p1/Afe79xx/Src/tiAfe79_basicFunctions.c][ti_afe79_afeSpiCheckWrapper][559]ERROR:addr[0x011F], lsb[0], msb[7], data[0x07] not matching with expected value[0x00]

AFE ID: 0[../src/app/bringup.c][AFE_Bringup][17570]ERROR:AFE FROM FILE Read Check Fail: 0x011f[0:7] = 0x0000

AFE ID: 0[../src/CAFE2p1/Afe79xx/Src/tiAfe79_basicFunctions.c][ti_afe79_afeSpiCheckWrapper][559]ERROR:addr[0x011E], lsb[0], msb[7], data[0x07] not matching with expected value[0x00]

AFE ID: 0[../src/app/bringup.c][AFE_Bringup][17576]ERROR:AFE FROM FILE Read Check Fail: 0x011e[0:7] = 0x0000

AFE ID: 0[../src/CAFE2p1/Afe79xx/Src/tiAfe79_basicFunctions.c][ti_afe79_afeSpiCheckWrapper][559]ERROR:addr[0x011D], lsb[0], msb[7], data[0x07] not matching with expected value[0x00]

AFE ID: 0[../src/app/bringup.c][AFE_Bringup][17582]ERROR:AFE FROM FILE Read Check Fail: 0x011d[0:7] = 0x0000

AFE ID: 0[../src/CAFE2p1/Afe79xx/Src/tiAfe79_basicFunctions.c][ti_afe79_afeSpiCheckWrapper][559]ERROR:addr[0x011C], lsb[0], msb[7], data[0x07] not matching with expected value[0x00]

AFE ID: 0[../src/app/bringup.c][AFE_Bringup][17588]ERROR:AFE FROM FILE Read Check Fail: 0x011c[0:7] = 0x0000

AFE ID: 0[../src/CAFE2p1/Afe79xx/Src/tiAfe79_basicFunctions.c][ti_afe79_afeSpiCheckWrapper][559]ERROR:addr[0x00A2], lsb[0], msb[7], data[0x00] not matching with expected value[0xAA]

AFE ID: 0[../src/app/bringup.c][AFE_Bringup][17600]ERROR:AFE FROM FILE Read Check Fail: 0x00a2[0:7] = 0x00aa

AFE ID: 0[../src/CAFE2p1/Afe79xx/Src/tiAfe79_basicFunctions.c][ti_afe79_afeSpiCheckWrapper][559]ERROR:addr[0x00A4], lsb[0], msb[7], data[0x00] not matching with expected value[0x55]

AFE ID: 0[../src/app/bringup.c][AFE_Bringup][17606]ERROR:AFE FROM FILE Read Check Fail: 0x00a4[0:7] = 0x0055
//END: Done reading the JESD RX states to check if link is established
//END: Device Config Complete
//START: Setting TDD Pin in override state and setting override values.
//END: Setting TDD Pin in override state and setting override values.
AFE_init end

If I execute the command “adcDacSync” again, AFE will report some error. As shown in the following figure:

SerDes AB PLL Loss of Lock  ： The error mentioned the PLL loss of serdes AB.   Do you have any suggestions for me to locate the program?

 Clock or voltage?

Is the reference clock of serdes PLL the same as Fdac? Our Fdac PLL is working normally.