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AFE7906: AFE7906: AFE79xx sysParams.jesdTxLaneMux ?

Suematsu Tatsuya
Prodigy 180 points
Part Number: AFE7906
Other Parts Discussed in Thread: LMK04828

AFE7906 has 4 lanes per ADC as shown in the figure.
Trying to connect.

sysParams.LMFSHdRx =["48410","48410","48410","48410"]
sysParams.jesdTxLaneMux = [4,5,0,1,2,3,6,7]

If the above settings are made, will the 4 lane connections be as shown below?

1STX = unused
2STX = unused
3STX = JESD_LANE0
4STX = JESD_LANE1
5STX = JESD_LANE2
6STX = JESD_LANE3
7STX = unused
8STX = unused

  • 0
    TI__Expert 5055 points

    Hi Tatsuya,

    Yes, for the parameters that you have decided above the lanes will be connected like in your image if the FB channels are disabled.

    You can also use the GUI that comes with the AFE79xx Latte to view the configuration as you can see in the image below. 

    After running your script, you can click on "Latte Mode" -> "GUI Mode" to enter the GUI.

    Then you can navigate to the "JESD_TX" tab like in the image below.

    And finally you need to click the "Refresh GUI" button on the top right corner to see your configuration updated in the GUI. The GUI should only be used to view your configuration.

    Best,

    Camilo

  • 0 in reply to Camilo Garcia Trujillo
    Prodigy 180 points

    As you taught me,
    After running your script, you can click on "Latte Mode" -> "GUI Mode" to enter the GUI.
    Even if you press the "Refresh GUI" button, the GUI display of "JESD_TX" is not updated.

    The version of AFE79xx I'm using is 2.0.5
    Is there any other manner?

    ########　AFE79xx Latte ##############################################
    setupParams.skipFpga = 1
    sysParams = AFE.systemParams
    setupParams.fpgaRefClk = 256 # Original 184.32
    AFE.systemStatus.loadTrims = 1 # Original 1

    ############## Top Level ##############
    sysParams.fbEnable = [False]*2 # Original [False]*2
    sysParams.FRef = 256 # Original 491.52
    sysParams.FadcRx = 1536 # Original 2949.12 sampling Clock
    sysParams.FadcFb = 1536 # Original 2949.12
    sysParams.Fdac = 1536 # Original 2949.12*3

    ###sysParams.adcSelect0 = [0,1,2] #Original default
    ###sysParams.adcSelect1 = [0,1,2] #Original default

    sysParams.enableDacInterleavedMode = False #DAC interleave mode to save power consumption. Fs/2 - Fin spur occurs
    # Original False
    sysParams.modeTdd = 0 # Original 0
    # 0- Single TDD Pin for all Channels
    # 1- Separate Control for 2T/2R/1F
    # 2- Separate Control for 1T/1R/1F

    ###sysParams.topLevelSystemMode = 'StaticTDDMode' # unused
    sysParams.RRFMode = 0 #Original 0 4T4R2F FDD mode
    sysParams.jesdSystemMode = [3,3] #ADC JESD Original [3,3]
    #SystemMode 0: 2R1F-FDD ; rx1-rx2-fb-fb
    #SystemMode 1: 1R1F-FDD ; rx1-rx1-fb-fb
    #SystemMode 2: 2R-FDD ; rx1-rx1-rx2-rx2
    #SystemMode 3: 1R ; rx1-rx1-rx1-rx1
    #SystemMode 4: 1F ; fb-fb-fb-fb
    #SystemMode 5: 1R1F-TDD ; rx1/fb-rx1/fb-rx1/fb-rx1/fb
    #SystemMode 8: 1R1F-TDD 1R-FDD (FB-2Lanes)(RX1 RX2 interchanged) ; rx2/fb-rx2/fb-rx1-rx1

    sysParams.jesdLoopbackEn = 0 #Make it 1 to Enable the JESDTX to JESDRX internal loopback
    #Original 0
    sysParams.LMFSHdRx =["48410","48410","48410","48410"] #ADC JESD
    # The 2nd and 4th are valid only for jesdSystemMode values in (2,6,7,8). For other modes, select 4 converter modes for 1st and 3rd.
    # Original ['44210', '44210', '44210', '44210']
    sysParams.LMFSHdFb = ["48410","48410"] #Original ["22210","22210"]
    sysParams.LMFSHdTx = ["48410","48410","48410","48410"] #DAC JESD
    #Original ["44210","44210","44210","44210"]



    sysParams.jesdTxProtocol = [0,0] #ADC JESD 8b/10b Original [2,2]
    sysParams.jesdRxProtocol = [0,0] #DAC JESD 8b/10b Original [2,2]
    sysParams.serdesFirmware TRUE # If you want to lead any firmware, please speify the path here. Otherwise it will not write any firmware
    #Original True

    ###sysParams.jesdTxLaneMux = [0,1,2,3,4,5,6,7] #ADC JESD Original [0,1,2,3,4,5,6,7]
    sysParams.jesdTxLaneMux = [4,5,0,1,2,3,6,7] #ADC JESD Original [0,1,2,3,4,5,6,7]
    # Enter which lanes you want in each location.
    # Note that across 2T Mux is not possible in 0.5.
    # For example, if you want to exchange the first two lines of each 2T, this should be [[1,0,2,3],[5,4,6,7]]
    sysParams.jesdRxLaneMux = [0,1,2,3,4,5,6,7] #DAC JESD Original [0,1,2,3,4,5,6,7]
    # Enter which lanes you want in each location.
    # Note that across 2R Mux is not possible in 0.5.
    # For example, if you want to exchange the first two lines of each 2R, this should be [[1,0,2,3],[5,4,6,7]]

    sysParams.jesdRxRbd = [4, 4] #DAC JESD Original [4, 4]

    # scrambler is disabled
    sysParams.rxJesdTxScr = [False]*4 #ADC JESD Original [False]*4
    sysParams.fbJesdTxScr = [False]*2 #Original [False]*2
    sysParams.jesdRxScr = [False]*4 #DAC JESD Original [False]*4

    sysParams.rxJesdTxK = [32,32,32,32]
    sysParams.fbJesdTxK = [32,32] #Original default
    sysParams.jesdRxK = [32,32,32,32] #Original default


    sysParams.ncoFreqMode = "FCW" #Original "1KHz"


    sysParams.txEnable = [False,False,False,False] # Original default


    sysParams.txNco0 = [[600,600], #Original [[5400,5400], #Band0, Band1 for TxA for NCO0
    [600,600], #Original [500,500], #Band0, Band1 for TxB for NCO0
    [600,600], #Original [2500,2500], #Band0, Band1 for TxC for NCO0
    [600,600]] #Original [1800,1800]] #Band0, Band1 for TxD for NCO0

    sysParams.rxNco0 = [[384,384], #Original [[5400,5400], #Band0, Band1 for RxA for NCO0
    [352,384], #Original [500,500], #Band0, Band1 for RxB for NCO0
    [608,384], #Original [2500,2500], #Band0, Band1 for RxC for NCO0
    [384,384]] #Original [1800,1800]] #Band0, Band1 for RxD for NCO0
    sysParams.fbNco0 = [384,384] #Original [500,1800] #FBA, FBC for NCO0


    sysParams.numBandsRx = [0]*4 #Original [0]*4 # 0 for single, 1 for dual
    sysParams.numBandsTx = [0,0,0,0]#Original [0,0,0,0]

    sysParams.ddcFactorRx = [6]*4 #Original [4]*4 # DDC decimation factor for RX A, B, C and D
    sysParams.ddcFactorFb = [6]*2 #Original [4]*2
    sysParams.ducFactorTx = [6]*4 #Original [12]*4

    AFE.systemStatus.loadTrims =1

    #####

    ## The following parameters sets up the LMK04828 clocking schemes
    lmkParams.pllEn = True #Original True #False
    lmkParams.inputClk = 10 # Original 1474.56#737.28 <-----VCXO Freq 122.88MHz x 12
    lmkParams.sysrefFreq = 4 #Original None Default 2949.12/1024
    lmkParams.lmkFrefClk = True # Original True
    lmkParams.lmkPulseSysrefMode = False #Original None
    lmkParams.lmkVcoFreq = 2560 #Original None Default 2949.12
    lmkParams.xtalFreq = 80 # Original None Default 122.88
    setupParams.fpgaRefClk = 256 # Original None

    ## The following parameters sets up the register and macro dumps
    logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
    logDumpInst.logFormat = 0x00
    logDumpInst.rewriteFile = 1
    logDumpInst.rewriteFileFormat4 = 1
    device.optimizeWrites = 0
    device.rawWriteLogEn = 1

    ######

    ## The following parameters sets up the SYNCIN and SYNCOUT to interface with the TSW14J57
    sysParams.jesdABLvdsSync = True # Original 1
    sysParams.jesdCDLvdsSync = True # Original 1
    sysParams.rxJesdTxSyncMux = [0,0,0,0]
    sysParams.fbJesdTxSyncMux = [0,0]
    sysParams.jesdRxSyncMux = [0,0,0,0] #[0,0,1,1]
    sysParams.syncLoopBack = True # Original True




    ## The following parameters sets up the GPIOs
    sysParams.gpioMapping={
    'H8': 'ADC_SYNC0',
    'H7': 'ADC_SYNC1',
    'N8': 'ADC_SYNC2',
    'N7': 'ADC_SYNC3',
    'H9': 'DAC_SYNC0',
    'G9': 'DAC_SYNC1',
    'N9': 'DAC_SYNC2',
    'P9': 'DAC_SYNC3',
    'P14': 'GLOBAL_PDN',
    'K14': 'FBABTDD',
    'R6': 'FBCDTDD',
    'H15': ['TXATDD','TXBTDD'],
    'V5': ['TXCTDD','TXDTDD'],
    'E7': ['RXATDD','RXBTDD'],
    'R15': ['RXCTDD','RXDTDD']}

    ## Initiates LMK04828 and AFE79xx Bring-up
    setupParams.skipLmk = FALSE
    AFE.initializeConfig()
    lmkParams.sysrefFreq = AFE.systemStatus.sysrefFreq
    AFE.LMK.lmkConfig()

    ############################################
    #====== Warning ==============================================
    #Executing .. Files/zcu102_LatteScripts_8b10b/Houtan_8b10b_4Lane_ConfigLmk.py
    #Start Time 2023-11-06 13:34:37.129000
    The External Sysref Frequency should be an integer factor of: 4.0MHz
    2T2R1F Number: 0
    Valid Configuration: True
    laneRateRx: 10240.0
    laneRateFb: 10240.0
    laneRateTx: 10240.0
    2T2R1F Number: 1
    Valid Configuration: True
    laneRateRx: 10240.0
    laneRateFb: 10240.0
    laneRateTx: 10240.0
    LMK Clock Divider - Device registers reset.
    LMK Clock Divider - Device registers reset.
    REFCLOCK is used from LMK source, ensure board connections are ok to do the same
    #Done executing .. Files/zcu102_LatteScripts_8b10b/Houtan_8b10b_4Lane_ConfigLmk.py
    #End Time 2023-11-06 13:34:37.819000
    #Execution Time = 0.69000005722 s
    #================ ERRORS:0, WARNINGS:1 ================#

  • 0 in reply to Suematsu Tatsuya
    TI__Expert 5055 points

    Hi Tatsuya,

    I believe I found the issue. It seems like there were a couple of problems with the script you posted that didn't let the GUI get updated. Below are the things I changed and the updated script:

    1. Line 39: sysParams.LMFSHdFb = ["24410","24410"] '''Changed from ["48410","48410"] to ["24410","24410"]''' because there is no 48410 mode for the FB channels
    2. Line 47: sysParams.serdesFirmware =True '''Changed from "TRUE" to "=True"'''
    3. Line 151: setupParams.skipLmk = False '''Changed from FALSE to False'''

    setupParams.skipFpga = 1
sysParams = AFE.systemParams
setupParams.fpgaRefClk = 256 # Original 184.32
AFE.systemStatus.loadTrims = 1 # Original 1

############## Top Level ##############
sysParams.fbEnable = [False]*2 # Original [False]*2
sysParams.FRef = 256 # Original 491.52
sysParams.FadcRx = 1536 # Original 2949.12 sampling Clock
sysParams.FadcFb = 1536 # Original 2949.12
sysParams.Fdac = 1536 # Original 2949.12*3

###sysParams.adcSelect0 = [0,1,2] #Original default
###sysParams.adcSelect1 = [0,1,2] #Original default

sysParams.enableDacInterleavedMode = False #DAC interleave mode to save power consumption. Fs/2 - Fin spur occurs
# Original False
sysParams.modeTdd = 0 # Original 0
# 0- Single TDD Pin for all Channels
# 1- Separate Control for 2T/2R/1F
# 2- Separate Control for 1T/1R/1F

###sysParams.topLevelSystemMode = 'StaticTDDMode' # unused
sysParams.RRFMode = 0 #Original 0 4T4R2F FDD mode
sysParams.jesdSystemMode = [3,3] #ADC JESD Original [3,3]
#SystemMode 0: 2R1F-FDD ; rx1-rx2-fb-fb
#SystemMode 1: 1R1F-FDD ; rx1-rx1-fb-fb
#SystemMode 2: 2R-FDD ; rx1-rx1-rx2-rx2
#SystemMode 3: 1R ; rx1-rx1-rx1-rx1
#SystemMode 4: 1F ; fb-fb-fb-fb
#SystemMode 5: 1R1F-TDD ; rx1/fb-rx1/fb-rx1/fb-rx1/fb
#SystemMode 8: 1R1F-TDD 1R-FDD (FB-2Lanes)(RX1 RX2 interchanged) ; rx2/fb-rx2/fb-rx1-rx1

sysParams.jesdLoopbackEn = 0 #Make it 1 to Enable the JESDTX to JESDRX internal loopback
#Original 0
sysParams.LMFSHdRx =["48410","48410","48410","48410"] #ADC JESD
# The 2nd and 4th are valid only for jesdSystemMode values in (2,6,7,8). For other modes, select 4 converter modes for 1st and 3rd.
# Original ['44210', '44210', '44210', '44210']
sysParams.LMFSHdFb = ["24410","24410"] '''Changed from ["48410","48410"] to ["24410","24410"]'''#Original ["22210","22210"] 
sysParams.LMFSHdTx = ["48410","48410","48410","48410"] #DAC JESD
#Original ["44210","44210","44210","44210"]



sysParams.jesdTxProtocol = [0,0] #ADC JESD 8b/10b Original [2,2]
sysParams.jesdRxProtocol = [0,0] #DAC JESD 8b/10b Original [2,2]
sysParams.serdesFirmware =True  '''Changed from "TRUE" to "=True"''' # If you want to lead any firmware, please speify the path here. Otherwise it will not write any firmware
#Original True

###sysParams.jesdTxLaneMux = [0,1,2,3,4,5,6,7] #ADC JESD Original [0,1,2,3,4,5,6,7]
sysParams.jesdTxLaneMux = [4,5,0,1,2,3,6,7] #ADC JESD Original [0,1,2,3,4,5,6,7]
# Enter which lanes you want in each location.
# Note that across 2T Mux is not possible in 0.5.
# For example, if you want to exchange the first two lines of each 2T, this should be [[1,0,2,3],[5,4,6,7]]
sysParams.jesdRxLaneMux = [0,1,2,3,4,5,6,7] #DAC JESD Original [0,1,2,3,4,5,6,7]
# Enter which lanes you want in each location.
# Note that across 2R Mux is not possible in 0.5.
# For example, if you want to exchange the first two lines of each 2R, this should be [[1,0,2,3],[5,4,6,7]]

sysParams.jesdRxRbd = [4, 4] #DAC JESD Original [4, 4]

# scrambler is disabled
sysParams.rxJesdTxScr = [False]*4 #ADC JESD Original [False]*4
sysParams.fbJesdTxScr = [False]*2 #Original [False]*2
sysParams.jesdRxScr = [False]*4 #DAC JESD Original [False]*4

sysParams.rxJesdTxK = [32,32,32,32]
sysParams.fbJesdTxK = [32,32] #Original default
sysParams.jesdRxK = [32,32,32,32] #Original default


sysParams.ncoFreqMode = "FCW" #Original "1KHz"


sysParams.txEnable = [False,False,False,False] # Original default


sysParams.txNco0 = [[600,600], #Original [[5400,5400], #Band0, Band1 for TxA for NCO0
[600,600], #Original [500,500], #Band0, Band1 for TxB for NCO0
[600,600], #Original [2500,2500], #Band0, Band1 for TxC for NCO0
[600,600]] #Original [1800,1800]] #Band0, Band1 for TxD for NCO0

sysParams.rxNco0 = [[384,384], #Original [[5400,5400], #Band0, Band1 for RxA for NCO0
[352,384], #Original [500,500], #Band0, Band1 for RxB for NCO0
[608,384], #Original [2500,2500], #Band0, Band1 for RxC for NCO0
[384,384]] #Original [1800,1800]] #Band0, Band1 for RxD for NCO0
sysParams.fbNco0 = [384,384] #Original [500,1800] #FBA, FBC for NCO0


sysParams.numBandsRx = [0]*4 #Original [0]*4 # 0 for single, 1 for dual
sysParams.numBandsTx = [0,0,0,0]#Original [0,0,0,0]

sysParams.ddcFactorRx = [6]*4 #Original [4]*4 # DDC decimation factor for RX A, B, C and D
sysParams.ddcFactorFb = [6]*2 #Original [4]*2
sysParams.ducFactorTx = [6]*4 #Original [12]*4

AFE.systemStatus.loadTrims =1

#####

## The following parameters sets up the LMK04828 clocking schemes
lmkParams.pllEn = True #Original True #False
lmkParams.inputClk = 10 # Original 1474.56#737.28 <-----VCXO Freq 122.88MHz x 12
lmkParams.sysrefFreq = 4 #Original None Default 2949.12/1024
lmkParams.lmkFrefClk = True # Original True
lmkParams.lmkPulseSysrefMode = False #Original None
lmkParams.lmkVcoFreq = 2560 #Original None Default 2949.12
lmkParams.xtalFreq = 80 # Original None Default 122.88
setupParams.fpgaRefClk = 256 # Original None

## The following parameters sets up the register and macro dumps
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat = 0x00
logDumpInst.rewriteFile = 1
logDumpInst.rewriteFileFormat4 = 1
device.optimizeWrites = 0
device.rawWriteLogEn = 1

######

## The following parameters sets up the SYNCIN and SYNCOUT to interface with the TSW14J57
sysParams.jesdABLvdsSync = True # Original 1
sysParams.jesdCDLvdsSync = True # Original 1
sysParams.rxJesdTxSyncMux = [0,0,0,0]
sysParams.fbJesdTxSyncMux = [0,0]
sysParams.jesdRxSyncMux = [0,0,0,0] #[0,0,1,1]
sysParams.syncLoopBack = True # Original True




## The following parameters sets up the GPIOs
sysParams.gpioMapping={
'H8': 'ADC_SYNC0',
'H7': 'ADC_SYNC1',
'N8': 'ADC_SYNC2',
'N7': 'ADC_SYNC3',
'H9': 'DAC_SYNC0',
'G9': 'DAC_SYNC1',
'N9': 'DAC_SYNC2',
'P9': 'DAC_SYNC3',
'P14': 'GLOBAL_PDN',
'K14': 'FBABTDD',
'R6': 'FBCDTDD',
'H15': ['TXATDD','TXBTDD'],
'V5': ['TXCTDD','TXDTDD'],
'E7': ['RXATDD','RXBTDD'],
'R15': ['RXCTDD','RXDTDD']}

## Initiates LMK04828 and AFE79xx Bring-up
setupParams.skipLmk = False  '''Changed from FALSE to False'''
AFE.initializeConfig()
lmkParams.sysrefFreq = AFE.systemStatus.sysrefFreq
AFE.LMK.lmkConfig()

############################################

    Please try the code above and let me know if you still do not see the GUI update.

    Best,

    Camilo