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AFE7900EVM: <--> TSW14J58EVM Device Bringup issues.

Part Number: AFE7900EVM
Other Parts Discussed in Thread: AFE8000EVM, TSW14J58EVM

#======
#Executing .. AFE7900/bringup/setup.py
#Start Time 2023-11-10 10:53:45.384000 
AFE79xxLibraryPG1p0
spi - USB Instrument created.
resetDevice
Purge
Kintex RegProgrammer - USB Instrument created.
Kintex RegProgrammer - USB Instrument created.
Kintex RegProgrammer - USB Instrument created.
FPGA reset - USB Instrument created.
#Done executing .. AFE7900/bringup/setup.py
#End Time 2023-11-10 10:53:55.074000
#Execution Time = 9.6899998188 s 
#================ ERRORS:0, WARNINGS:0 ================#
#======
#Executing .. AFE7900/bringup/devInit.py
#Start Time 2023-11-10 10:54:00.314000 
Power Card - USB Instrument created.
Version : 0x101204c
Connected to Capture Card
Loaded Libraries
Refreshed GUI
#Done executing .. AFE7900/bringup/devInit.py
#End Time 2023-11-10 10:54:30.187000
#Execution Time = 29.873000145 s 
#================ ERRORS:0, WARNINGS:0 ================#
#======
#Executing .. AFE7900/bringup/S1_OnboardClk_RX_250M_TX_FB_500M.py
#Start Time 2023-11-10 10:55:42.100000 
The External Sysref Frequency should be an integer factor of: 3.84MHz
2T2R1F Number: 0
Valid Configuration: True
laneRateRx: 9830.4
laneRateFb: 9830.4
laneRateTx: 9830.4
2T2R1F Number: 1
Valid Configuration: True
laneRateRx: 9830.4
laneRateFb: 9830.4
laneRateTx: 9830.4
LMK Clock Divider - Device registers reset.
LMK Clock Divider - Device registers reset.
REFCLOCK is used from LMK source, ensure board connections are ok to do the same
Resetting FPGA.
Version : 0x101204c
Connected to Capture Card
Mismatch in the FPGA bit file version. AFE JESD Protocol is 204B but the FPGA bit file is 0x204c
LMK and FPGA Configured.
DONOT_OPEN_Atharv_FULL - Device registers reset.
chipType: 0xa
chipId: 0x78
chipVersion: 0x20
AFE Reset Done
Fuse farm load autoload done successful
No autload error
Fuse farm load autoload done successful
No autload error
patchSize=6677
//Patch Version = 155
//PG Version = 0
//Release Date [dd/mm/yy] = 27/11/21
AFE MCU Wake up done and patch loaded.
PLL Locked
AFE PLL Configured.
AFE SerDes Configured.
AFE Digital Chains configured.
AFE TX Analog configured.
AFE RX Analog configured.
AFE FB Analog configured.
AFE JESD configured.
AFE AGC configured.
AFE GPIO configured.
Sysref Read as expected
###########Device DAC JESD-RX 0 Link Status###########
LOS Indicator for (Serdes Loss of signal) lane 0: 1
Serdes-FIFO error for lane 0: 1
LOS Indicator for (Serdes Loss of signal) lane 1: 1
Serdes-FIFO error for lane 1: 1
LOS Indicator for (Serdes Loss of signal) lane 2: 1
Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane2: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane3: False; Please check if the transmitter is sending data and eye is good.
CS State TX0: 0b00000000 . It is expected to be 0b10101010
FS State TX0: 0b00000000 . It is expected to be 0b01010101
Couldn't get the link up for device RX: 0; Alarms: 0x3700
###################################
###########Device DAC JESD-RX 1 Link Status###########
LOS Indicator for (Serdes Loss of signal) lane 0: 1
Serdes-FIFO error for lane 0: 1
LOS Indicator for (Serdes Loss of signal) lane 1: 1
Serdes-FIFO error for lane 1: 1
LOS Indicator for (Serdes Loss of signal) lane 2: 1
Serdes-FIFO error for lane 2: 1
LOS Indicator for (Serdes Loss of signal) lane 3: 1
Serdes-FIFO error for lane 3: 1
Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane2: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane3: False; Please check if the transmitter is sending data and eye is good.
CS State TX0: 0b00000000 . It is expected to be 0b10101010
FS State TX0: 0b00000000 . It is expected to be 0b01010101
Couldn't get the link up for device RX: 1; Alarms: 0xff00
###################################
AFE Configuration Complete
#Done executing .. AFE7900/bringup/S1_OnboardClk_RX_250M_TX_FB_500M.py
#End Time 2023-11-10 10:56:31.520000
#Execution Time = 49.4200000763 s 
#================ ERRORS:24, WARNINGS:1 ================#

Hello,

I am Currently Tring to follow the AFE79xxEVM_TSW14J58_Bringup powerpoint and am having issues getting it going.

Hardware:

AFE8000EVM (5VDC 5A max)

TSW14J58EVM (5VDC 5A max)

Jumpers:

J21: 1-2

J29: 1-2

J30: 1-2

J34: 2-3

J35: 1-2 

Software:

AFE79xx

3 USB connections to SS ports

Power connections checked

Worth noting I am having a similar issue with the AFE8000EVM board with a Live issue:

AFE8000EVM: <--> TSW14J58EVM SYSREF, NOT aligned causing no lane locking - RF & microwave forum - RF & microwave - TI E2E support forums

Thank you in advance for the advice.

Kind regards

Oliver Forbes-Shaw

  • Hi Oliver,

    From the log you have posted, I can see that the error you are getting is because the script you are running is for JESD204B 8b10b encoding, but the FPGA firmware you are using is for JESD204C 64b66b encoding. Which is why you get the error "Mismatch in the FPGA bit file version. AFE JESD Protocol is 204B but the FPGA bit file is 0x204c"

    Could you try removing jumper J35 before powering the TSW14J58EVM to set it to JESD204B 8b10b which matches the script you are trying to run? and then follow the guide again?

    Best,

    Camilo

  • Thank you Camilo.
    Apologies for the late reply, my time was diverted else where temporarily. This has solved the issue to get the hardware up and running.