AFE7950EVM: Custom sample rate with data rate setting

Youngho Suh

Part Number: AFE7950EVM
Other Parts Discussed in Thread: TRF1208, AFE7950,

Hi,
I plan to test AFE7950 ADC with RF=3.55GHz (12MHz BW) input with your default setup (2949.12MSPS) with EVM (no TRF1208 option) interfaced with ZCU102 FPGA. I have several progressive questions.

1) NCO
At Latte, under "AFE7950 --> bringup", what NCO number do you recommend to put for 3.55GHz RF input? Do you recommend NCO of 3550MHz to put this into DC? Since this ADC uses sub-samples inherently, I wondered that the NCO number identical to RF input will still work. From your Frequency Planner spreadsheet, I found NCO of 588.88MHz put Alias centered at 6MHz for 12MHz BW signal. Will this NCO number still be good?

2) Decimation change
With the same configuration as 1), but if I want to change decimation to 48 so that the data rate changed to 61.44MHz, what else need to be changed. Do I need to change FPGA/JESD frequency? If so, can you please advise how can this be done?

3) Finally, I would like to have custom sample rate with 156.25MHz reference clock as follows.
Ref. clock: 156.25MHz
ADC Sample rate: 2500MSPS
Decimation: 20
NCO: 1044MHz (TBD, please recommend the NCO)
Output data rate: 125Mbps

To achieve this, I consider direct feed of 156.25MHzthough J13 (REF_CLK_LOW) to achieve 2500MSPS and decimation 20 will make data rate of 125MSPS. Now the question will be do you have an example file to implement this? If not, can you please provide one? I believe this will need to change FPGA/JESD data clock that needs LMK to be reconfigured. Please advise this. Or, if you think replacing onboard 120.88MHz with 15.625MHz XO is better for this test, please advise this either.

Many thanks in advance.

Youngho

over 1 year ago

0 Youngho Suh over 1 year ago

Intellectual 540 points

can anyone answer this? How and where do we configure LMK at the AFE7950EVM at Latte to get new 156.25MHz output? I consider to swap 122.88MHz VCXO with 156.25MHz one to produce 156.25MHz clock toward AFE7950. Also need to change FPGA and JESD clock rate but don't know how.

0 David Chaparro over 1 year ago in reply to Youngho Suh

TI__Genius 17891 points

Hi Youngho,

If you would like to use a reference frequency of 156.25MHz there are two methods that can be followed.

The first, which does not require board modifications, is to provide the LMK with an external clock that can be divided down to provide the 156.25MHz as well as the FPGA clock. The script below has been configured such that the LMK should be given a 625MHz clock, at 5dBm, through SMA J14, LMK_CLK_IN. The 625MHz clock is divided down to 156.25MHz for the AFE and 125MHz for the FPGA clock.

I updated the NCOs to 3520MHz in the script so that you can capture the 3550Mhz tone.

Fullscreen AFE7950_4T4R_125M.py Download

##############		Read me			##############
#In HSDC Pro DAC tab, Select AFE79xx_2x2TX_24410; Data Rate = 125M
#In HSDC Pro ADC tab, Select AFE79xx_2x2RX_24410; Data Rate = 125M ---> To capture 4 RX channels

sysParams=AFE.systemParams
sysParams.__init__();sysParams.chipVersion=chipVersion

setupParams.skipFpga = 1 # setup FPGA (TSW14J56) using HSDC Pro 
##############		Top Level			##############
sysParams.FRef			= 156.25
sysParams.FadcRx		= 2500
sysParams.FadcFb		= 2500
sysParams.Fdac			= 2500*4
sysParams.externalClockRx=False
sysParams.externalClockTx=False
													
##############		Digital Chain		##############

		#####	RX	#####
sysParams.ddcFactorRx	=	[20,20,20,20]				#DDC decimation factor for RX A, B, C and D
sysParams.rxNco0		= 	[[3520,9500],			#Band0, Band1 for RXA 
							[3520,9500],        	#Band0, Band1 for RXB 
							[3520,9500],        	#Band0, Band1 for RXC 
							[3520,9500]]        	#Band0, Band1 for RXD 

		#####	FB	#####
sysParams.fbEnable		=	[False,False]
sysParams.ddcFactorFb	=	[6,6]					#DDC decimation factor for FB 1 and 2
sysParams.fbNco0		= 	[9500,9500]				#Band0 for FB1 and FB2 

		#####	TX	#####
sysParams.ducFactorTx	=	[80,80,80,80]			#DUC interpolation factor for TX A, B, C and D
sysParams.txNco0		= 	[[9500,9500],			#Band0, Band1 for TXA 
							[9500,9500],        	#Band0, Band1 for TXB 
							[9500,9500],        	#Band0, Band1 for TXC 
							[9500,9500]]        	#Band0, Band1 for TXD


##############		JESD		##############

		#####	ADC-JESD	#####
sysParams.jesdSystemMode= [3,3]
													#SystemMode 0:	2R1F-FDD						; rx1-rx2-fb -fb
													#SystemMode 1:	1R1F-FDD						; rx -rx -fb -fb
													#SystemMode 2:	2R-FDD							; rx1-rx1-rx2-rx2
													#SystemMode 3:	1R								; rx -rx -rx -rx
													#SystemMode 4:	1F								; fb -fb- fb -fb
													#SystemMode 5:	1R1F-TDD						; rx/fb-rx/fb-rx/fb-rx/fb
													
sysParams.jesdTxProtocol= [0,0]						# 0 - 8b/10b encoding; 2 - 64b/66b encoding 
sysParams.LMFSHdRx		= ["24410","24410","24410","24410"]
													# The 2nd and 4th are valid only for jesdSystemMode values in (0,2).
													# For other modes, select 4 converter modes for 1st and 3rd.
sysParams.LMFSHdFb		= ["22210","22210"]

sysParams.rxJesdTxScr	= [True,True,True,True]
sysParams.fbJesdTxScr	= [True,True]

sysParams.rxJesdTxK		= [16,16,16,16]
sysParams.fbJesdTxK		= [16,16]

sysParams.jesdTxLaneMux	= [0,1,2,3,4,5,6,7]			# Enter which lanes you want in each location. 
													# For example, if you want to exchange the first two lines of each 2T,
													#		this should be [[1,0,2,3],[5,4,6,7]]

		#####	DAC-JESD	#####
sysParams.jesdRxProtocol= [0,0]
sysParams.LMFSHdTx		= ["24410","24410","24410","24410"]
sysParams.jesdRxLaneMux	= [0,1,2,3,4,5,6,7]			# Enter which lanes you want in each location.
													# For example, if you want to exchange the first two lines of each 2R
													#		this should be [[1,0,2,3],[5,4,6,7]]
sysParams.jesdRxRbd		= [4, 4]
sysParams.jesdRxScr		= [True,True,True,True]
sysParams.jesdRxK		= [16,16,16,16]

		#####	JESD Common	#####

sysParams.jesdABLvdsSync= True
sysParams.jesdCDLvdsSync= True
sysParams.syncLoopBack	= True	#JESD Sync signal is connected to FPGA

##############		GPIO		##############
sysParams.gpioMapping	= {
						'H8': 'ADC_SYNC0',
						'H7': 'ADC_SYNC1',
						'N8': 'ADC_SYNC2',
						'N7': 'ADC_SYNC3',
						'H9': 'DAC_SYNC0',
						'G9': 'DAC_SYNC1',
						'N9': 'DAC_SYNC2',
						'P9': 'DAC_SYNC3',
						'P14': 'GLOBAL_PDN',
						'K14': 'FBABTDD',
						'R6': 'FBCDTDD',
						'H15': ['TXATDD','TXBTDD'],
						'V5': ['TXCTDD','TXDTDD'],
						'E7': ['RXATDD','RXBTDD'],
						'R15': ['RXCTDD','RXDTDD']}

##############		LMK Params		##############
lmkParams.pllEn			= True
lmkParams.inputClk		= 625 # Valid only when lmkParams.pllEn = False
lmkParams.lmkFrefClk	= True
setupParams.fpgaRefClk	= 125 # Should be equal to LaneRate/40 for TSW14J56
lmkParams.xtalFreq = 156.25
lmkParams.lmkVcoFreq=2500


##############		Logging		##############
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat=0x0 #Modify to 0x1 to save register scequence to log file. Script takes more time to execute.
logDumpInst.rewriteFile=1
logDumpInst.rewriteFileFormat4=1
device.optimizeWrites=0
device.rawWriteLogEn=1
lmk.rawWriteLogEn=1

device.delay_time = 0
#-------------------------------------------------------------------------------------------------#
AFE.deviceBringup()

AFE.TOP.overrideTdd(15,3,15)	# bit-wise; 4R,2F,4T

The second method is to replace the 122.88MHz VCXO with the 156.25MHz VCXO, as you mentioned. With this method you would then need to update the LMK parameters, shown below, so that the correct VCO frequency is used.

lmkParams.pllEn			= True
lmkParams.inputClk		= 625 # Valid only when lmkParams.pllEn = False
lmkParams.lmkFrefClk	= True
setupParams.fpgaRefClk	= 125 # Should be equal to LaneRate/40 for TSW14J56
lmkParams.xtalFreq = 156.25
lmkParams.lmkVcoFreq=2500

Regards,

David Chaparro

0 Youngho Suh over 1 year ago in reply to David Chaparro

Intellectual 540 points

Hello David,

The code you gave me has "no PLL lock" error until I change "setupParams.fpgaRefClk = 500" and "sysParams.FRef = 500". Now PLL locks but produced SerDes error.

Here is the code that I used for your review. The error message will follow after that. FYI, I plan to use 4xADC and 4xDAC, 8 lanes. Please check LMFSHd setting either.

##############		Read me			##############
#In HSDC Pro DAC tab, Select AFE79xx_2x2TX_24410; Data Rate = 125M
#In HSDC Pro ADC tab, Select AFE79xx_2x2RX_24410; Data Rate = 125M ---> To capture 4 RX channels

sysParams=AFE.systemParams
sysParams.__init__();sysParams.chipVersion=chipVersion

setupParams.skipFpga = 1 # setup FPGA (TSW14J56) using HSDC Pro 
##############		Top Level			##############
setupParams.fpgaRefClk	= 500 # Should be equal to LaneRate/40 for TSW14J56
sysParams.FRef			= 500 # 
#sysParams.FRef			= 625
sysParams.FadcRx		= 2500
sysParams.FadcFb		= 2500
sysParams.Fdac			= 2500*4
sysParams.externalClockRx=False
sysParams.externalClockTx=False
													
##############		Digital Chain		##############

		#####	RX	#####
sysParams.ddcFactorRx	=	[20,20,20,20]				#DDC decimation factor for RX A, B, C and D
sysParams.rxNco0		= 	[[3520,9500],			#Band0, Band1 for RXA 
							[3520,9500],        	#Band0, Band1 for RXB 
							[3520,9500],        	#Band0, Band1 for RXC 
							[3520,9500]]        	#Band0, Band1 for RXD 

		#####	FB	#####
sysParams.fbEnable		=	[False,False]
sysParams.ddcFactorFb	=	[6,6]					#DDC decimation factor for FB 1 and 2
sysParams.fbNco0		= 	[9500,9500]				#Band0 for FB1 and FB2 

		#####	TX	#####
sysParams.ducFactorTx	=	[80,80,80,80]			#DUC interpolation factor for TX A, B, C and D
sysParams.txNco0		= 	[[9500,9500],			#Band0, Band1 for TXA 
							[9500,9500],        	#Band0, Band1 for TXB 
							[9500,9500],        	#Band0, Band1 for TXC 
							[9500,9500]]        	#Band0, Band1 for TXD


##############		JESD		##############

		#####	ADC-JESD	#####
sysParams.jesdSystemMode= [3,3]
													#SystemMode 0:	2R1F-FDD						; rx1-rx2-fb -fb
													#SystemMode 1:	1R1F-FDD						; rx -rx -fb -fb
													#SystemMode 2:	2R-FDD							; rx1-rx1-rx2-rx2
													#SystemMode 3:	1R								; rx -rx -rx -rx
													#SystemMode 4:	1F								; fb -fb- fb -fb
													#SystemMode 5:	1R1F-TDD						; rx/fb-rx/fb-rx/fb-rx/fb
													
sysParams.jesdTxProtocol= [0,0]						# 0 - 8b/10b encoding; 2 - 64b/66b encoding 
#sysParams.LMFSHdRx		= ["24410","24410","24410","24410"]
sysParams.LMFSHdRx		= ["48410","48410","48410","48410"]
													# The 2nd and 4th are valid only for jesdSystemMode values in (0,2).
													# For other modes, select 4 converter modes for 1st and 3rd.
sysParams.LMFSHdFb		= ["22210","22210"]

sysParams.rxJesdTxScr	= [True,True,True,True]
sysParams.fbJesdTxScr	= [True,True]

sysParams.rxJesdTxK		= [16,16,16,16]
sysParams.fbJesdTxK		= [16,16]

sysParams.jesdTxLaneMux	= [0,1,2,3,4,5,6,7]			# Enter which lanes you want in each location. 
													# For example, if you want to exchange the first two lines of each 2T,
													#		this should be [[1,0,2,3],[5,4,6,7]]

		#####	DAC-JESD	#####
sysParams.jesdRxProtocol= [0,0]
#sysParams.LMFSHdTx		= ["24410","24410","24410","24410"]
sysParams.LMFSHdTx		= ["48410","48410","48410","48410"]
sysParams.jesdRxLaneMux	= [0,1,2,3,4,5,6,7]			# Enter which lanes you want in each location.
													# For example, if you want to exchange the first two lines of each 2R
													#		this should be [[1,0,2,3],[5,4,6,7]]
sysParams.jesdRxRbd		= [4, 4]
sysParams.jesdRxScr		= [True,True,True,True]
sysParams.jesdRxK		= [16,16,16,16]

		#####	JESD Common	#####

sysParams.jesdABLvdsSync= True
sysParams.jesdCDLvdsSync= True
sysParams.syncLoopBack	= True	#JESD Sync signal is connected to FPGA

##############		GPIO		##############
sysParams.gpioMapping	= {
						'H8': 'ADC_SYNC0',
						'H7': 'ADC_SYNC1',
						'N8': 'ADC_SYNC2',
						'N7': 'ADC_SYNC3',
						'H9': 'DAC_SYNC0',
						'G9': 'DAC_SYNC1',
						'N9': 'DAC_SYNC2',
						'P9': 'DAC_SYNC3',
						'P14': 'GLOBAL_PDN',
						'K14': 'FBABTDD',
						'R6': 'FBCDTDD',
						'H15': ['TXATDD','TXBTDD'],
						'V5': ['TXCTDD','TXDTDD'],
						'E7': ['RXATDD','RXBTDD'],
						'R15': ['RXCTDD','RXDTDD']}

##############		LMK Params		##############
lmkParams.xtalFreq = 156.25
lmkParams.lmkVcoFreq=2500
lmkParams.pllEn			= True
lmkParams.inputClk		= 625 # Valid only when lmkParams.pllEn = False
lmkParams.lmkFrefClk	= True




##############		Logging		##############
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat=0x0 #Modify to 0x1 to save register scequence to log file. Script takes more time to execute.
logDumpInst.rewriteFile=1
logDumpInst.rewriteFileFormat4=1
device.optimizeWrites=0
device.rawWriteLogEn=1
lmk.rawWriteLogEn=1

device.delay_time = 0
#-------------------------------------------------------------------------------------------------#
AFE.deviceBringup()

AFE.TOP.overrideTdd(15,3,15)	# bit-wise; 4R,2F,4T

The error message I got is as follows.

PLL Locked
AFE PLL Configured.
AFE SerDes Configured.
AFE Digital Chains configured.
AFE TX Analog configured.
AFE RX Analog configured.
AFE FB Analog configured.
AFE JESD configured.
AFE AGC configured.
AFE GPIO configured.
Sysref Read as expected
###########Device DAC JESD-RX 0 Link Status###########
Serdes-FIFO error for lane 0: 1
Serdes-FIFO error for lane 1: 1
Serdes-FIFO error for lane 2: 1
Serdes-FIFO error for lane 3: 1
Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane2: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane3: False; Please check if the transmitter is sending data and eye is good.
CS State TX0: 0b00000000 . It is expected to be 0b10101010
FS State TX0: 0b00000000 . It is expected to be 0b01010101
Couldn't get the link up for device RX: 0; Alarms: 0xf000
###################################
AFE Configuration Complete
#Done executing .. AFE7950/bringup/TI_IP_ConfigAfe.py
#End Time 2023-12-14 12:22:36.515000
#Execution Time = 35.131000042 s 
#================ ERRORS:9, WARNINGS:1 ================#

Thank you.

0 David Chaparro over 1 year ago in reply to Youngho Suh

TI__Genius 17891 points

Hi Youngho,

The error that you are showing points to an issue with the FPGA. Can you confirm that the FPGA has been configured and is sending data before configuring the AFE. Also, the FPGA clock should be equivalent to LaneRate/40 when using the TSW14J56/57.

Regards,

David Chaparro

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AFE7950EVM: Custom sample rate with data rate setting