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Part Number: AFE7950EVM
Other Parts Discussed in Thread: AFE7950,
Hello, team
Can I use the AFE7950 alone without the FPGA board？
I connected the EVM board with usb interface under latte，after bring up， and run mode5，the current of the EVM is about 1.1A, but the loopback function dosenot work， the DAC output noting.
I tested RXA-TXA and RXB-TXB, none of them work.
so I want to know can the EVM board work in loopback mode without FPGA board.
hello,
Add some information
The J14 of EVM board is sourced by 491.52MHz 0dBm clk, the log file is as below。 the latte version is updated to TI-AFE79xx-Latte_V2p0p7-Installer
after run initalization, the supply current only got a bit addition from 0.65A to 0.75A, it looks like the pll of AFE7950 is not worked
#====== #Executing .. AFE7950/bringup/setup.py #Start Time 2023-11-24 14:57:13.269000 AFE79xxLibraryPG1p0 spi - USB Instrument created. resetDevice Purge Kintex RegProgrammer - USB Instrument created. Kintex RegProgrammer - USB Instrument created. Kintex RegProgrammer - USB Instrument created. #Done executing .. AFE7950/bringup/setup.py #End Time 2023-11-24 14:57:20.675000 #Execution Time = 7.40599989891 s #================ ERRORS:0, WARNINGS:0 ================# #====== #Executing .. AFE7950/bringup/devInit.py #Start Time 2023-11-24 14:57:28.420000 Power Card - USB Instrument created. Reset the FPGA and try again. Loaded Libraries Refreshed GUI #Done executing .. AFE7950/bringup/devInit.py #End Time 2023-11-24 14:57:49.242000 #Execution Time = 20.8220000267 s #================ ERRORS:1, WARNINGS:0 ================# #====== #Executing .. AFE7950/bringup/S5_OnboardClk_RX_TX_250M_10Gbps_4Lanes.py #Start Time 2023-11-24 14:58:12.772000 The External Sysref Frequency should be an integer factor of: 3.84MHz 2T2R1F Number: 0 Valid Configuration: True laneRateRx: 9830.4 laneRateFb: 9830.4 laneRateTx: 9830.4 2T2R1F Number: 1 Valid Configuration: True laneRateRx: 9830.4 laneRateFb: 9830.4 laneRateTx: 9830.4 LMK Clock Divider - Device registers reset. LMK Clock Divider - Device registers reset. REFCLOCK is used from LMK source, ensure board connections are ok to do the same LMK and FPGA Configured. DONOT_OPEN_Atharv_FULL - Device registers reset. chipType: 0xa chipId: 0x78 chipVersion: 0x11 AFE Reset Done Fuse farm load autoload done successful No autload error Fuse farm load autoload done successful No autload error //Firmware Version = 11000 //PG Version = 1 //Release Date [dd/mm/yy] = 10/7/19 patchSize=11697 //Patch Version = 165 //PG Version = 0 //Release Date [dd/mm/yy] = 27/11/21 AFE MCU Wake up done and patch loaded. PLL Locked AFE PLL Configured. Waiting for MACRO_READY bit to go high, Count: 1 Waiting for MACRO_READY bit to go high, Count: 2 Waiting for MACRO_READY bit to go high, Count: 3 Waiting for MACRO_READY bit to go high, Count: 4 Waiting for MACRO_READY bit to go high, Count: 5 Waiting for MACRO_READY bit to go high, Count: 6 Waiting for MACRO_READY bit to go high, Count: 7 Waiting for MACRO_READY bit to go high, Count: 8 Waiting for MACRO_READY bit to go high, Count: 9 Waiting for MACRO_READY bit to go high, Count: 10 Waiting for MACRO_READY bit to go high, Count: 11 Waiting for MACRO_READY bit to go high, Count: 12 Waiting for MACRO_READY bit to go high, Count: 13 Waiting for MACRO_READY bit to go high, Count: 14 Waiting for MACRO_READY bit to go high, Count: 15 Waiting for MACRO_READY bit to go high, Count: 16 Waiting for MACRO_READY bit to go high, Count: 17 Waiting for MACRO_READY bit to go high, Count: 18 Waiting for MACRO_READY bit to go high, Count: 19 Waiting for MACRO_READY bit to go high, Count: 20 Waiting for MACRO_READY bit to go high failed Waiting for MACRO_DONE bit to go high, Count: 1 Waiting for MACRO_DONE bit to go high, Count: 2 Waiting for MACRO_DONE bit to go high, Count: 3 Waiting for MACRO_DONE bit to go high, Count: 4 Waiting for MACRO_DONE bit to go high, Count: 5 Waiting for MACRO_DONE bit to go high, Count: 6 Waiting for MACRO_DONE bit to go high, Count: 7 Waiting for MACRO_DONE bit to go high, Count: 8 Waiting for MACRO_DONE bit to go high, Count: 9 Waiting for MACRO_DONE bit to go high, Count: 10 Waiting for MACRO_DONE bit to go high, Count: 11 Waiting for MACRO_DONE bit to go high, Count: 12 Waiting for MACRO_DONE bit to go high, Count: 13 Waiting for MACRO_DONE bit to go high, Count: 14 Waiting for MACRO_DONE bit to go high, Count: 15 Waiting for MACRO_DONE bit to go high, Count: 16 Waiting for MACRO_DONE bit to go high, Count: 17 Waiting for MACRO_DONE bit to go high, Count: 18 Waiting for MACRO_DONE bit to go high, Count: 19 Waiting for MACRO_DONE bit to go high, Count: 20 Waiting for MACRO_DONE bit to go high failed Waiting for MACRO_READY bit to go high, Count: 1 Waiting for MACRO_READY bit to go high, Count: 2 Waiting for MACRO_READY bit to go high, Count: 3 Waiting for MACRO_READY bit to go high, Count: 4 Waiting for MACRO_READY bit to go high, Count: 5 Waiting for MACRO_READY bit to go high, Count: 6 Waiting for MACRO_READY bit to go high, Count: 7 Waiting for MACRO_READY bit to go high, Count: 8 Waiting for MACRO_READY bit to go high, Count: 9 Waiting for MACRO_READY bit to go high, Count: 10 Waiting for MACRO_READY bit to go high, Count: 11 Waiting for MACRO_READY bit to go high, Count: 12 Waiting for MACRO_READY bit to go high, Count: 13 Waiting for MACRO_READY bit to go high, Count: 14 Waiting for MACRO_READY bit to go high, Count: 15 Waiting for MACRO_READY bit to go high, Count: 16 Waiting for MACRO_READY bit to go high, Count: 17 Waiting for MACRO_READY bit to go high, Count: 18 Waiting for MACRO_READY bit to go high, Count: 19 Waiting for MACRO_READY bit to go high, Count: 20 Waiting for MACRO_READY bit to go high failed Waiting for MACRO_DONE bit to go high, Count: 1 Waiting for MACRO_DONE bit to go high, Count: 2 Waiting for MACRO_DONE bit to go high, Count: 3 Waiting for MACRO_DONE bit to go high, Count: 4 Waiting for MACRO_DONE bit to go high, Count: 5 Waiting for MACRO_DONE bit to go high, Count: 6 Waiting for MACRO_DONE bit to go high, Count: 7 Waiting for MACRO_DONE bit to go high, Count: 8 Waiting for MACRO_DONE bit to go high, Count: 9 Waiting for MACRO_DONE bit to go high, Count: 10 Waiting for MACRO_DONE bit to go high, Count: 11 Waiting for MACRO_DONE bit to go high, Count: 12 Waiting for MACRO_DONE bit to go high, Count: 13 Waiting for MACRO_DONE bit to go high, Count: 14 Waiting for MACRO_DONE bit to go high, Count: 15 Waiting for MACRO_DONE bit to go high, Count: 16 Waiting for MACRO_DONE bit to go high, Count: 17 Waiting for MACRO_DONE bit to go high, Count: 18 Waiting for MACRO_DONE bit to go high, Count: 19 Waiting for MACRO_DONE bit to go high, Count: 20 Waiting for MACRO_DONE bit to go high failed
then I replaced the supply wire, now the supply current get to 2.55A, but the loopback function still can't work
there are 14 errors in log file as below
#====== #Executing .. AFE7950/bringup/setup.py #Start Time 2023-11-25 09:52:44.575000 AFE79xxLibraryPG1p0 spi - USB Instrument created. resetDevice Purge Kintex RegProgrammer - USB Instrument created. Kintex RegProgrammer - USB Instrument created. Kintex RegProgrammer - USB Instrument created. #Done executing .. AFE7950/bringup/setup.py #End Time 2023-11-25 09:52:51.163000 #Execution Time = 6.58800005913 s #================ ERRORS:0, WARNINGS:0 ================# #====== #Executing .. AFE7950/bringup/devInit.py #Start Time 2023-11-25 09:52:53.087000 Power Card - USB Instrument created. Reset the FPGA and try again. Loaded Libraries Error Loading iGui #Done executing .. AFE7950/bringup/devInit.py #End Time 2023-11-25 09:53:10.114000 #Execution Time = 17.0270001888 s #================ ERRORS:2, WARNINGS:0 ================# #====== #Executing .. AFE7950/bringup/S5_OnboardClk_RX_TX_250M_10Gbps_4Lanes.py #Start Time 2023-11-25 09:53:22.206000 The External Sysref Frequency should be an integer factor of: 3.84MHz 2T2R1F Number: 0 Valid Configuration: True laneRateRx: 9830.4 laneRateFb: 9830.4 laneRateTx: 9830.4 2T2R1F Number: 1 Valid Configuration: True laneRateRx: 9830.4 laneRateFb: 9830.4 laneRateTx: 9830.4 LMK Clock Divider - Device registers reset. LMK Clock Divider - Device registers reset. REFCLOCK is used from LMK source, ensure board connections are ok to do the same LMK and FPGA Configured. DONOT_OPEN_Atharv_FULL - Device registers reset. chipType: 0xa chipId: 0x78 chipVersion: 0x11 AFE Reset Done Fuse farm load autoload done successful No autload error Fuse farm load autoload done successful No autload error //Firmware Version = 11000 //PG Version = 1 //Release Date [dd/mm/yy] = 10/7/19 patchSize=11697 //Patch Version = 165 //PG Version = 0 //Release Date [dd/mm/yy] = 27/11/21 AFE MCU Wake up done and patch loaded. PLL Locked AFE PLL Configured. AFE SerDes Configured. AFE Digital Chains configured. AFE TX Analog configured. AFE RX Analog configured. AFE FB Analog configured. AFE JESD configured. AFE AGC configured. AFE GPIO configured. Sysref Read as expected ###########Device DAC JESD-RX 0 Link Status########### LOS Indicator for (Serdes Loss of signal) lane 0: 1 Serdes-FIFO error for lane 0: 1 LOS Indicator for (Serdes Loss of signal) lane 1: 1 Serdes-FIFO error for lane 1: 1 Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good. Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good. CS State TX0: 0b00000000 . It is expected to be 0b00001010 FS State TX0: 0b00000000 . It is expected to be 0b00000101 Couldn't get the link up for device RX: 0; Alarms: 0x3300 ################################### ###########Device DAC JESD-RX 1 Link Status########### LOS Indicator for (Serdes Loss of signal) lane 0: 1 Serdes-FIFO error for lane 0: 1 LOS Indicator for (Serdes Loss of signal) lane 1: 1 Serdes-FIFO error for lane 1: 1 Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good. Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good. CS State TX0: 0b00000000 . It is expected to be 0b00001010 FS State TX0: 0b00000000 . It is expected to be 0b00000101 Couldn't get the link up for device RX: 1; Alarms: 0x3300 ################################### AFE Configuration Complete #Done executing .. AFE7950/bringup/S5_OnboardClk_RX_TX_250M_10Gbps_4Lanes.py #End Time 2023-11-25 09:53:56.047000 #Execution Time = 33.8409998417 s #================ ERRORS:14, WARNINGS:1 ================#
Hi Xiao,
The AFE7950EVM should be powered from a power supply capable of 5V, 5A. If there is a lot of loss on the power cable then you made need to increase the voltage 5.5V.
In order to use the AFE EVM without an FPGA the AFE can be configured into loopback mode where the ADC data is looped back to the DAC. The script below has been modified for this loopback mode.
############## Read me ##############
#In HSDC Pro DAC tab, Select AFE79xx_2x2TX_44210; Data Rate = 491.52M
#In HSDC Pro ADC tab, Select AFE79xx_2x2RX_44210; Data Rate = 491.52M ---> To capture 4 RX channels
sysParams=AFE.systemParams
sysParams.__init__();sysParams.chipVersion=chipVersion
setupParams.skipFpga = 1 # setup FPGA (TSW14J56) using HSDC Pro
############## Top Level ##############
sysParams.FRef = 491.52
sysParams.FadcRx = 2949.12
sysParams.FadcFb = 2949.12
sysParams.Fdac = 2949.12*4
sysParams.externalClockRx=False
sysParams.externalClockTx=False
############## Digital Chain ##############
##### RX #####
sysParams.ddcFactorRx = [6,6,6,6] #DDC decimation factor for RX A, B, C and D
sysParams.rxNco0 = [[9500,9500], #Band0, Band1 for RXA
[9500,9500], #Band0, Band1 for RXB
[9500,9500], #Band0, Band1 for RXC
[9500,9500]] #Band0, Band1 for RXD
##### FB #####
sysParams.fbEnable = [False,False]
sysParams.ddcFactorFb = [6,6] #DDC decimation factor for FB 1 and 2
sysParams.fbNco0 = [9500,9500] #Band0 for FB1 and FB2
##### TX #####
sysParams.ducFactorTx = [24,24,24,24] #DUC interpolation factor for TX A, B, C and D
sysParams.txNco0 = [[9500,9500], #Band0, Band1 for TXA
[9500,9500], #Band0, Band1 for TXB
[9500,9500], #Band0, Band1 for TXC
[9500,9500]] #Band0, Band1 for TXD
############## JESD ##############
##### ADC-JESD #####
sysParams.jesdSystemMode= [3,3]
#SystemMode 0: 2R1F-FDD ; rx1-rx2-fb -fb
#SystemMode 1: 1R1F-FDD ; rx -rx -fb -fb
#SystemMode 2: 2R-FDD ; rx1-rx1-rx2-rx2
#SystemMode 3: 1R ; rx -rx -rx -rx
#SystemMode 4: 1F ; fb -fb- fb -fb
#SystemMode 5: 1R1F-TDD ; rx/fb-rx/fb-rx/fb-rx/fb
sysParams.jesdTxProtocol= [0,0] # 0 - 8b/10b encoding; 2 - 64b/66b encoding
sysParams.LMFSHdRx = ["44210","44210","44210","44210"]
# The 2nd and 4th are valid only for jesdSystemMode values in (0,2).
# For other modes, select 4 converter modes for 1st and 3rd.
sysParams.LMFSHdFb = ["22210","22210"]
sysParams.rxJesdTxScr = [True,True,True,True]
sysParams.fbJesdTxScr = [True,True]
sysParams.rxJesdTxK = [16,16,16,16]
sysParams.fbJesdTxK = [16,16]
sysParams.jesdTxLaneMux = [0,1,2,3,4,5,6,7] # Enter which lanes you want in each location.
# For example, if you want to exchange the first two lines of each 2T,
# this should be [[1,0,2,3],[5,4,6,7]]
##### DAC-JESD #####
sysParams.jesdRxProtocol= [0,0]
sysParams.LMFSHdTx = ["44210","44210","44210","44210"]
sysParams.jesdRxLaneMux = [0,1,2,3,4,5,6,7] # Enter which lanes you want in each location.
# For example, if you want to exchange the first two lines of each 2R
# this should be [[1,0,2,3],[5,4,6,7]]
sysParams.jesdRxRbd = [4, 4]
sysParams.jesdRxScr = [True,True,True,True]
sysParams.jesdRxK = [16,16,16,16]
##### JESD Common #####
sysParams.jesdABLvdsSync= True
sysParams.jesdCDLvdsSync= True
sysParams.syncLoopBack = False #JESD Sync signal is connected to FPGA
sysParams.jesdLoopbackEn= True
############## GPIO ##############
sysParams.gpioMapping = {
'H8': 'ADC_SYNC0',
'H7': 'ADC_SYNC1',
'N8': 'ADC_SYNC2',
'N7': 'ADC_SYNC3',
'H9': 'DAC_SYNC0',
'G9': 'DAC_SYNC1',
'N9': 'DAC_SYNC2',
'P9': 'DAC_SYNC3',
'P14': 'GLOBAL_PDN',
'K14': 'FBABTDD',
'R6': 'FBCDTDD',
'H15': ['TXATDD','TXBTDD'],
'V5': ['TXCTDD','TXDTDD'],
'E7': ['RXATDD','RXBTDD'],
'R15': ['RXCTDD','RXDTDD']}
############## LMK Params ##############
lmkParams.pllEn = True
lmkParams.inputClk = 983.04 # Valid only when lmkParams.pllEn = False
lmkParams.lmkFrefClk = True
setupParams.fpgaRefClk = 245.76 # Should be equal to LaneRate/40 for TSW14J56
############## Logging ##############
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat=0x0 #Modify to 0x1 to save register scequence to log file. Script takes more time to execute.
logDumpInst.rewriteFile=1
logDumpInst.rewriteFileFormat4=1
device.optimizeWrites=0
device.rawWriteLogEn=1
device.delay_time = 0
#-------------------------------------------------------------------------------------------------#
AFE.deviceBringup()
AFE.TOP.overrideTdd(15,3,15) # bit-wise; 4R,2F,4T
The App Note that is linked below has more information on this mode.
https://www.ti.com/lit/an/sbaa525a/sbaa525a.pdf
Regards,
David Chaparro