Hi experts:
I used xilinx's JESD204 IP core and encountered the following image when sending data and I'm not seeing any signal from the TXA,.(I'm only using two TX ports and the configuration is also below).
And I have other questions
1. I did not add another delay, please ask how to add XDC delay file, is there a specific example (especially sysref and sync) (because I did not find the VC model of the FPGA routine).
2. Since I am sending data, how can I determine my center frequency (since my oscilloscope can only observe 1000M)?
