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AFE7950: multi chip sync

David Park
Expert 6630 points
Part Number: AFE7950
Other Parts Discussed in Thread: LMK04828, LMX2820

Hi,

When 48 of AFE7950 is adopted in 1 system, there are many FPGAs.

In this case, how can the system performs synchronization of 48u of AFE7950?

Beamformer IC, any software or any clocking?

Thanks.

  • 0
    Prodigy 10 points

    System can be configured Several Stage of FPGA . (Number of stage is depend on FPGA's I/O and Performance capability)

    On 1st stage of FPGA, Several AFE7950 can be connect to FPGA with JESD204B I/F to gathering data from AFE chipset.

    On 2nd Stage of FPGA, if there's many FPGA on 1st stage of FPGA, 2nd Stage FPGA's will gather data from 1st stage FPGA.

    ...

    ...

     Finally, All data will be aggregated to 1 MPSOC (SOM) FPGA board .

    At this point, All AFE chipset should be synchronized for Simultaneous Process for RF side. 

    As I know, sevel AFE which connected to FPGA directrly in one board can be synchronized using LMK04828 (for example). 

    But, IF 1st stage's FPGAs is configured to Different board, how can we do synchroniz between 1st stage FPGA's boards.

    Finally. All AFE chipset should be syncronized to scan target, How can we configure all synchronization?

  • 0
    TI__Genius 17671 points

    Hi David,

    The reference design below shows how the TI clocking parts can be used to clock multiple AFEs. This can be used as a reference. 

    https://www.ti.com/tool/TIDA-010230 

    Regards,

    David Chaparro 

  • 0 in reply to David Chaparro
    Prodigy 40 points

    Hi David,
    Thanks for reply.

    In the reference design the LMX2820 devices provide DCLK (8847.36MHz) to AFE7950 devices and internal VCO of AFE7950 is not used. Is it correct?

    Is multichip RF phase synchronization among several AFE7950 possible by external SYSREF signal only and using internal VCO of AFE7950 to generate DAC clock? 

    Regards,
    Vladimir

  • 0 in reply to Vladimir Nesterov
    TI__Genius 17671 points

    Hi Vladimir,

    In this reference design the AFEs were using an external clock of 8847.36MHz and the internal PLL was not being used. 

    If you plan to use the AFEs internal PLL then you can still synchronize multiple AFEs using the SYSREF signal. It would actually be easier to meet the SYSREF setup and hold times with the AFE Fref, as it will be a lower frequency. 

    Regards,

    David Chaparro