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AFE7950EVM: AFE7950EVM

Vitor Cristina
Prodigy 60 points
Part Number: AFE7950EVM

Hello,

I'm following the texas indications to generate the Vivado project for the reference design named "ZCU102_AFE79xx_64b66b_12Gbps". I have access to the TI_204c_CoreIP. As indicated by Texas I have created a new project where I have loaded the CoreIP and all the .sv, .vh and .xci files to the desing sources of my project (and the constraint file to).

I have synthetized, implemented and generated the bitstream file. I don´t get any error, but I get always the same critical warning: "[Constraints 18-1056] Clock 'fpga_ref_clk' completely overrides clock 'sys_clk_p'.
New: create_clock -period 6.400 -name fpga_ref_clk [get_ports sys_clk_p]".

Anyways, I try to program my board with the bit file and the ltx file and it programs but it doesn´t open the hw_ilas and the hw_vios tabs, as it opens when I program the board with the bit file that Texas provides. Can you tell me why does this happens? If I have the same project as you, it should generate the same bit file and it should give the same results. Also, isn´t more simple to give us acces to your Vivado project (folder with .xpr file) instead of the .sv, .xci, files? Because, I can never guarantee that I have the same project as you to generate the bit file. 

This is what I get by programming with Texas bit file of the ZCU102_AFE79xx_64b66b_12Gbps project:

And this is what I get by programming with the bit file generated by the project created by me:

As you can see, I don´t get acces to the hw_ilas and hw_vios tabs and i get more than one warning saying that the debug core was not detected.

Another important note is that if we try to use the TI_204c_IP Core with another Version of Vivado besides 2019.1, the TI_204c_IP_xilinx.svp appears as <hidden>, while in Vivado 2019.1 it assumes the name of the module TI_204c_IP. This sould be important to include in Texas documentation...I didn´t see this referenced on the user guide. 

I have been trying to generate this project for a long time...I hope that someone can help. 

Thank you 

  • 0
    TI__Genius 17831 points

    Hi Vitor,

    One thing that I have noticed is that for the reference design that was provided the clock should be 184.32MHz. The constraints file, clocking wizard, and transceiver wizard should all already set for this clock. Can you confirm this is set correctly in your project?

    Also, just to confirm is the AFE connected to the HPC1 connector of the ZCU102? 

    Regards,

    David Chaparro

  • 0 in reply to David Chaparro
    Prodigy 60 points

    Hello, 

    The clock for the  reference designs is defined to 156.25 MHz, not 184.32 MHz as you can see in the constarints file that was provided by you to this reference design as I show above:

    And yes I am connecting the AFE to the HPC1 connector of ZCU102.

    Regards,

    Vitor Cristina

  • 0 in reply to Vitor Cristina
    TI__Genius 17831 points

    Hi Vitor,

    The comment is incorrect and the frequency should be 184.32MHz. The FPGA reference clock was set to LaneRate/80, which comes out to be 184.32MHz. The timing constraints that were in the file by default were setup for 184.32MHz. I would recommend using the exact files that were provided without any changes in order to verify the provided design on your setup. 

    I have tested using the files from the 'ZCU102_AFE79xx_64b66b_12Gbps' zipped folder and I was able to create a bit file that had no issues when running on the ZCU102. One thing to make sure is that when before loading the firmware on the FPGA the AFE7950EVM should be configured to provide the clocks, as shown in the instructions provided.

    Regards,

    David chaparro

  • 0 in reply to David Chaparro
    Prodigy 60 points

    Hi David,

    Thank you for the reply. When your team gave me access to the TI204C-IP Core (the zipped folder named 'TI204C-IP-Release-v1.11-LATEST') I saw that there was a folder named 'reference_designs'. When I open this folder there are several folders with the name of the different reference designs. One of them is called 'zcu102_64b66b' which I supposed that it was the same example as 'ZCU102_AFE79xx_64b66b_12Gbps' so I used the IP and RTL files from this folder. But it happens that they are not equal. The constraints file from the 'zcu102_64b66b' is the one with the information that I mentioned in the first place.

    This constraints in fact are different from the 'ZCU102_AFE79xx_64b66b_12Gbps' zipped folder.

    Can you confirm this?

    Thank you,

    Vitor

  • +1 in reply to Vitor Cristina
    TI__Genius 17831 points

    Hi Vitor,

    The reference design folder (in the zipped folder named 'TI204C-IP-Release-v1.11-LATEST') contains only loopback reference designs that should be tested with the loopback card provided with the Xilinx dev kit.

    The AFE79xx specific designs are available in the AFE79xx secore folder under the folder named '5-TI_JESD204_IP_REF_DESIGNS'. The project files that should be used can be found in the 'ZCU102_AFE79xx_64b66b_12Gbps' zipped folder. 

    Please use only the files found in the 'ZCU102_AFE79xx_64b66b_12Gbps' zipped folder and see if this fixes the issues you are facing. 

    Regards,

    David Chaparro 

  • 0 in reply to David Chaparro
    Prodigy 60 points

    Thank you, this resolved my issue. Can you tell if there is any limitation in de frequency of txNCO that is defined in the file 'TI_IP_12Gbps_8Lane_ConfigLmk.py' ? I'm asking this because I was not able to transmit in a frequency of 9.5GHz. The maximum was about 8GHz. I have only chenged this .py file in the parameter 'sysParams.txNco0'.

  • 0 in reply to Vitor Cristina
    TI__Genius 17831 points

    Hi Vitor,

    The only limits should be the ones given in the datasheet, 600Mhz - 12Ghz. 

    What output do you see when you try the 9.5GHz NCO? Also, just to confirm are you using the latest version of the AFE79xx software?

    Regards,

    David Chaparro