Hello,
We are in the process of migrating your reference design (44210 operating in non-deterministic latency mode) to our custom FPGA board.
For the same we were looking at how the GTH transceiver is configured and noticed the following (screenshot follows):
1) Quad X1Y2 uses the refclock from Quad X1Y3 while Quad X1Y1 uses MGTREFCLK0. This seems odd, X1Y2 could have used the refclock from the quad below (X1Y1). May I ask you to please help us understand.
2) In another reference design 42220 which has deterministic latency, the refclock distribution makes more sense here. Please advise on the selection of the master channel (its different in the two cases for the same FPGA board).
We have an older version of TI IP user guide which does not have section 6.8 (deterministic latency) which you had asked us to refer to in an earlier discussion. We have asked for a renewal of our access to the IP.
Thank you for your help,
