AFE7950: AFE7950 use mode

Hi Xiao,

Return-to-Complement (RTC) or Mixed Mode is for 2nd Nyquist operation. To use the mixed mode in the AFE7950 DAC all that is needed is to have the DAC NCO frequencies (txNco0) greater than Fdac/2 (In the second Nyquist) when bringing up the device.

The bringup sequence will then recognize that you are trying to operate in second Nyquist and the mixed mode will be used. Note that the mixer frequencies of all the bands and NCOs should be in the same Nyquist.

For more information you can refer to this video: https://www.ti.com/video/5577272810001 

Best,

Camilo

Hi Xiao,

In this case your Fdac = 11796.48MHz so your Nyquist boundary is at Fdac/2 = 5,898.24MHz.

Since your txNco0 = 10000MHz which is greater than Fdac/2 but less than Fdac you are operating in the second Nyquist zone. And therefore the AFE DAC will be programmed to use the Mixed Mode.

Hopefully this makes it clear.

Best,

Camilo

Hi Xiao,

The AFE7950 supports interpolation and digital up conversion options that deliver up to 1200 MHz of signal bandwidth for four TX or 2400 MHz when using only two TX. This signal bandwidth is after the 80% passband of the interpolation block.

The signal bandwidth for the DAC is equal to (Fs/INT)*0.8 where “Fs” is the sampling rate of the DAC, “INT” is the interpolation factor, and “0.8” is the passband of the interpolation block.

But in your example, when your interface rate is 491.52MHz to the DAC. Your signal bandwidth will be 0.8*491.52 = 393.216MHz because of the passband of the interpolation filters.

Best,

Camilo

Hi Xiao,

If the DAC sampling rate (Fs) is fixed. The only other way to increase the signal bandwidth would be by reducing the interpolation rate. Which in turn increases the interface rate. 

The increase in interface rate means an increase in lane rate, but this can be adjusted for by changing things like the LMFS mode.

Best,

Camilo

Hi Xiao,

The 8b10b encoding in not recommended for lane rates above 16Gbps. And decreasing the ducFactorTx to 12 would give you a lane rate of 19.6608Gbps.

For more information on calculating lane rate see please see this post: https://e2e.ti.com/support/rf-microwave-group/rf-microwave/f/rf-microwave-forum/1202826/afe7950evm-lane-rate-calculation/4536527?tisearch=e2e-sitesearch&keymatch=calculate%252520lane%252520rate#4536527 

So the two options for the configuration would be the following:

1. Change to 64b66b encoding which will both decrease the lane rate and increase the lane rate limit. See configuration below as example:

##############		Read me			##############
#In HSDC Pro DAC tab, Select AFE79xx_2x2TX_44210; Data Rate = 983.04M
#In HSDC Pro ADC tab, Select AFE79xx_2x2RX_44210; Data Rate = 983.04M ---> To capture 4 RX channels

sysParams=AFE.systemParams
sysParams.__init__();sysParams.chipVersion=chipVersion

setupParams.skipFpga = 0 # setup FPGA (TSW14J56) using HSDC Pro 
##############		Top Level			##############
sysParams.FRef			= 491.52
sysParams.FadcRx		= 2949.12
sysParams.FadcFb		= 2949.12
sysParams.Fdac			= 2949.12*4
sysParams.externalClockRx=False
sysParams.externalClockTx=False
													
##############		Digital Chain		##############

sysParams.RRFMode		= 5					# RRF 0: 4T4R2F FDD Mode

		#####	RX	#####
sysParams.ddcFactorRx	=	[3,3,3,3]				#DDC decimation factor for RX A, B, C and D
sysParams.rxNco0		= 	[[9500,9500],			#Band0, Band1 for RXA 
							[9500,9500],        	#Band0, Band1 for RXB 
							[9500,9500],        	#Band0, Band1 for RXC 
							[9500,9500]]        	#Band0, Band1 for RXD 

		#####	FB	#####
sysParams.fbEnable		=	[False,False]
sysParams.ddcFactorFb	=	[3,3]					#DDC decimation factor for FB 1 and 2
sysParams.fbNco0		= 	[9500,9500]					#Band0 for FB1 and FB2 

		#####	TX	#####
sysParams.ducFactorTx	=	[12,12,12,12]			#DUC interpolation factor for TX A, B, C and D
sysParams.txNco0		= 	[[9500,9500],			#Band0, Band1 for TXA 
							[9500,9500],        	#Band0, Band1 for TXB 
							[9500,9500],        	#Band0, Band1 for TXC 
							[9500,9500]]        	#Band0, Band1 for TXD 


##############		JESD		##############

		#####	ADC-JESD	#####
sysParams.jesdSystemMode= [3,3]
													#SystemMode 0:	2R1F-FDD						; rx1-rx2-fb -fb
													#SystemMode 1:	1R1F-FDD						; rx -rx -fb -fb
													#SystemMode 2:	2R-FDD							; rx1-rx1-rx2-rx2
													#SystemMode 3:	1R								; rx -rx -rx -rx
													#SystemMode 4:	1F								; fb -fb- fb -fb
													#SystemMode 5:	1R1F-TDD						; rx/fb-rx/fb-rx/fb-rx/fb
													
sysParams.jesdTxProtocol= [2,2]						# 0 - 8b/10b encoding; 2 - 64b/66b encoding 
sysParams.LMFSHdRx		= ["44210","44210","44210","44210"]
													# The 2nd and 4th are valid only for jesdSystemMode values in (0,2).
													# For other modes, select 4 converter modes for 1st and 3rd.
sysParams.LMFSHdFb		= ["22210","22210"]

sysParams.rxJesdTxScr	= [False,False,False,False]
sysParams.fbJesdTxScr	= [False,False]

sysParams.rxJesdTxK		= [1,1,1,1]
sysParams.fbJesdTxK		= [1,1]

sysParams.jesdTxLaneMux	= [0,1,2,3,4,5,6,7]			# Enter which lanes you want in each location. 
													# For example, if you want to exchange the first two lines of each 2T,
													#		this should be [[1,0,2,3],[5,4,6,7]]

		#####	DAC-JESD	#####
sysParams.jesdRxProtocol= [2,2] # 0 - 8b/10b encoding; 2 - 64b/66b encoding 
sysParams.LMFSHdTx		= ["44210","44210","44210","44210"]
sysParams.jesdRxLaneMux	= [0,1,2,3,4,5,6,7]			# Enter which lanes you want in each location.
													# For example, if you want to exchange the first two lines of each 2R
													#		this should be [[1,0,2,3],[5,4,6,7]]
sysParams.jesdRxRbd		= [4, 4]
sysParams.jesdRxScr		= [False,False,False,False]
sysParams.jesdRxK		= [1,1,1,1]

		#####	JESD Common	#####
	
sysParams.jesdABLvdsSync= True
sysParams.jesdCDLvdsSync= True
sysParams.syncLoopBack	= 0	#JESD Sync signal is connected to FPGA

##############		GPIO		##############
sysParams.gpioMapping	= {
						'H8': 'ADC_SYNC0',
						'H7': 'ADC_SYNC1',
						'N8': 'ADC_SYNC2',
						'N7': 'ADC_SYNC3',
						'H9': 'DAC_SYNC0',
						'G9': 'DAC_SYNC1',
						'N9': 'DAC_SYNC2',
						'P9': 'DAC_SYNC3',
						'P14': 'GLOBAL_PDN',
						'K14': 'FBABTDD',
						'R6': 'FBCDTDD',
						'H15': ['TXATDD','TXBTDD'],
						'V5': ['TXCTDD','TXDTDD'],
						'E7': ['RXATDD','RXBTDD'],
						'R15': ['RXCTDD','RXDTDD']}

##############		LMK Params		##############
lmkParams.pllEn			= True
lmkParams.inputClk		= 983.04 # Valid only when lmkParams.pllEn = False
lmkParams.lmkFrefClk	= True
setupParams.fpgaRefClk	= 245.76 # Should be equal to LaneRate/40 for TSW14J56

##############		Logging		##############
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat=0x0 #Modify to 0x1 to save register scequence to log file. Script takes more time to execute.
logDumpInst.rewriteFile=1
logDumpInst.rewriteFileFormat4=1
device.optimizeWrites=0
device.rawWriteLogEn=1

device.delay_time = 0
#-------------------------------------------------------------------------------------------------#
AFE.deviceBringup()

AFE.TOP.overrideTdd(15,0,15)	# bit-wise; 4R,2F,4T

2. Disable two of the TX channels to half the lane rate if you must use 8b10b encoding. See configuration below as example:

##############		Read me			##############
#In HSDC Pro DAC tab, Select AFE79xx_2x1TX_42220; Data Rate = 983.04M
#In HSDC Pro ADC tab, Select AFE79xx_2x1RX_42220; Data Rate = 983.04M ---> To capture 4 RX channels

sysParams=AFE.systemParams
sysParams.__init__();sysParams.chipVersion=chipVersion

setupParams.skipFpga = 1 # setup FPGA (TSW14J56) using HSDC Pro 
##############		Top Level			##############
sysParams.FRef			= 491.52
sysParams.FadcRx		= 2949.12
sysParams.FadcFb		= 2949.12
sysParams.Fdac			= 2949.12*4
sysParams.externalClockRx=False
sysParams.externalClockTx=False
sysParams.RRFMode		= 5					# RRF 0: 4T4R2F FDD Mode
sysParams.enableDacInterleavedMode=False
													
##############		Digital Chain		##############

		#####	RX	#####
sysParams.rxEnable = [True,False,True,False]
sysParams.ddcFactorRx	=	[3]*4					#DDC decimation factor for RX A, B, C and D
sysParams.rxNco0		= 	[[9500,9500],			#Band0, Band1 for RXA 
							[9500,9500],        	#Band0, Band1 for RXB 
							[9500,9500],        	#Band0, Band1 for RXC 
							[9500,9500]]        	#Band0, Band1 for RXD 

		#####	FB	#####
sysParams.ddcFactorFb	=	[3]*2					#DDC decimation factor for FB 1 and 2
sysParams.fbNco0		= 	[9500,9500]				#Band0 for FB1 and FB2 
sysParams.fbEnable		=	[False,False]

		#####	TX	#####
sysParams.txEnable = [False,True,False,True]
sysParams.ducFactorTx	=	[12]*4					#DUC interpolation factor for TX A, B, C and D
sysParams.txNco0		= 	[[9500,9500],			#Band0, Band1 for TXA 
							[9500,9500],        	#Band0, Band1 for TXB 
							[9500,9500],        	#Band0, Band1 for TXC 
							[9500,9500]]        	#Band0, Band1 for TXD 
sysParams.txDataMux		= [2,3,0,1,6,7,4,5]	


##############		JESD		##############

		#####	ADC-JESD	#####
sysParams.jesdSystemMode= [3,3]
													#SystemMode 0:	2R1F-FDD						; rx1-rx2-fb -fb
													#SystemMode 1:	1R1F-FDD						; rx -rx -fb -fb
													#SystemMode 2:	2R-FDD							; rx1-rx1-rx2-rx2
													#SystemMode 3:	1R								; rx -rx -rx -rx
													#SystemMode 4:	1F								; fb -fb- fb -fb
													#SystemMode 5:	1R1F-TDD						; rx/fb-rx/fb-rx/fb-rx/fb
													
sysParams.jesdTxProtocol= [0,0]						# 0 - 8b/10b encoding; 2 - 64b/66b encoding 
sysParams.LMFSHdRx		= ["42220"]*4
													# The 2nd and 4th are valid only for jesdSystemMode values in (0,2).
													# For other modes, select 4 converter modes for 1st and 3rd.
sysParams.LMFSHdFb		= ["22210","22210"]

sysParams.rxJesdTxScr	= [True,True,True,True]
sysParams.fbJesdTxScr	= [True,True]

sysParams.rxJesdTxK		= [16,16,16,16]
sysParams.fbJesdTxK		= [16,16]

sysParams.jesdTxLaneMux	= [0,1,2,3,4,5,6,7]			# Enter which lanes you want in each location. 
													# For example, if you want to exchange the first two lines of each 2T,
													#		this should be [[1,0,2,3],[5,4,6,7]]

		#####	DAC-JESD	#####
sysParams.jesdRxProtocol= [0,0]
sysParams.LMFSHdTx		= ["42220"]*4
sysParams.jesdRxLaneMux	= [0,1,2,3,4,5,6,7]			# Enter which lanes you want in each location.
													# For example, if you want to exchange the first two lines of each 2R
													#		this should be [[1,0,2,3],[5,4,6,7]]
sysParams.jesdRxRbd		= [4, 4]
sysParams.jesdRxScr		= [True,True,True,True]
sysParams.jesdRxK		= [16,16,16,16]

		#####	JESD Common	#####
	
sysParams.jesdABLvdsSync= True
sysParams.jesdCDLvdsSync= True
sysParams.syncLoopBack	= True	#JESD Sync signal is connected to FPGA

##############		GPIO		##############
sysParams.gpioMapping	= {
						'H8': 'ADC_SYNC0',
						'H7': 'ADC_SYNC1',
						'N8': 'ADC_SYNC2',
						'N7': 'ADC_SYNC3',
						'H9': 'DAC_SYNC0',
						'G9': 'DAC_SYNC1',
						'N9': 'DAC_SYNC2',
						'P9': 'DAC_SYNC3',
						'P14': 'GLOBAL_PDN',
						'K14': 'FBABTDD',
						'R6': 'FBCDTDD',
						'H15': ['TXATDD','TXBTDD'],
						'V5': ['TXCTDD','TXDTDD'],
						'E7': ['RXATDD','RXBTDD'],
						'R15': ['RXCTDD','RXDTDD']}

##############		LMK Params		##############
lmkParams.pllEn			= True
lmkParams.inputClk		= 983.04 # Valid only when lmkParams.pllEn = False
lmkParams.lmkFrefClk	= True
setupParams.fpgaRefClk	= 245.76 # Should be equal to LaneRate/40 for TSW14J56

##############		Logging		##############
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat=0x0
logDumpInst.rewriteFile=1
logDumpInst.rewriteFileFormat4=1
device.optimizeWrites=0
device.rawWriteLogEn=1

device.delay_time = 0
#-------------------------------------------------------------------------------------------------#
# AFE.initializeConfig()
AFE.deviceBringup()

AFE.TOP.overrideTdd(15,3,15)	# bit-wise; 4R,2F,4T

If you have a configuration file I could change it for you.

Best,

Camilo