AFE7903: Buggy sysParams.txDataMux

Hi Christian,

I have tried this and I do not see an output out of the DAC when using the sysParams.txDataMux = [2,3,6,7,0,1,4,5] setting and having only TXB and TXD enabled.

I will reach out to the software team so that they can advise.

In the meantime, could you please post your configuration to make sure everything else is correct and so that we can test the same use case?

Best,

Camilo

Hi Camilo

I will send you the configuration in a private message. It contains to much project specific comments to post it in public.

Hi Christian, 

Thank you, we will make sure to review and get back to you with the advise from the software team.

Best,

Camilo

Hi Christian, 

Thank you for the patience. The correct setting should be sysParams.txDataMux = [6,7,0,1,4,5,2,3]. I have tried this and was able to see the correct output out of both TX channels.

Best,

Camilo

Hi Christian,

I've unlocked this thread so that we can continue discussion on this topic. I understand you and Camilo have had some further discussion - would you mind please describing what the current issue is and what we can do to help? 

Thanks!

Aman

Hi Aman

For me it seems that the configureDacDataMux() of the mJesdSubchip.py is buggy. I played with the registers and have now some correct values. Maybe not everything is correct, but I get the correct loopback routing. I'm now using the logic DataMux settings and added some raw register settings. 

sysParams.rxDataMux		= [0,1,4,5,2,3,6,7]
sysParams.txDataMux		= [2,3,6,7,0,1,4,5]

#Fix wrong muxes set by sysParams.txDataMux
#Gain access to JESD_SUBCHIP
AFE.regs.writeReg(0x0016,0x10)
#fix TXB
AFE.regs.writeReg(0x00ce,0x00)
AFE.regs.writeReg(0x0060,0x00)
#fix TXD
AFE.regs.writeReg(0x00d2,0x22)
AFE.regs.writeReg(0x0061,0x11)
#Release access to JESD_SUBCHIP
AFE.regs.writeReg(0x0016,0x10)

At the moment I use these settings and it works. But maybe I'm missing some registers.

Hi Christian,

Thanks for updating me on this. Would you mind please clarifying which lanes you want to appear together in the link? I see in the top post that you would like RX 1 and 3 on the same lane for STX and TX 2 and 4 on the same lane for SRX.

I also see that Camilo had provided this: sysParams.txDataMux = [6,7,0,1,4,5,2,3] - did this solution still give mixed-up signals at the FPGA?

Thanks!

Aman

Hi Aman

As we use the the AFE7903 we only have two channels. We would like to use both with just one lane. RX1 -> TX2 and RX3 -> TX4

Every solution either leads to mixed up channels or a unused but necessary second lane which we don't have.

And yes, the sysParams.txDataMux = [6,7,0,1,4,5,2,3]  together with sysParams.rxDataMux = [0,1,4,5,2,3,6,7] gives a mixed-up signals. That's how it should be with this setting (0,1 to 6,7 / RX1 to TX4)

Regards

Christian

Hi Christian,

Understood, thanks for the info. As I said, I'm working through these issues in order of priority, so I appreciate your patience on this issue. I will be sure to update you once I get have something to share.

Thanks,

Aman