Part Number: AFE7444EVM
hi Everybody,
I have been using AFE444 EVM for about 6 months now. In the last two weeks, the board have developed a new behavior which affects the phase of the signals. To be more precise, the phase between the signal input and output is not zero. I have been using the same signal, and the same setup which gave me god results in the past. I was able to shift these signal to zero by Matlab after capturing the signal. This solution would be perfect if I were sure the PLL of the output is the one that is causing he issue. However, I got the idea that the PLL at the input is the one that is broken assuming that there are separate PLL for input and output. I am really confused now, and I don't know if I am following the right procedure to get the right phase, or it is supposed to be at zero phase by default.
Also, the shift is not constant every time for the same setup, and signal. It varies every time we capture a new signal. The below result are acquired using the same setup, and signal.
