AFE7951: Clocking and synchronization of multiple devices

Hi,

My question is about clocking and phase synchronization between multiple devices:

I want to:

1. Deliver an external REF CLOCK of 12GHz to the DAC
2. Bypass the PLL
3. Divide the the external REF CLOCK by 4 to provide the sampling clock for the ADC (3GHz).

Question:

1. Can the divider of the ADC clock be synchronized across multiple devices? As per my knowledge a divider has a random phase upon power up, therefore multiple devices are not synchronized. 
2. The data sheet says that the N-divider can be synchronized by SYSREF. Question:
   1. Which divider is it:
      1. PLL REFCLK divider?
      2. PLL loop back integer divider?
      3. ADC/DAC clock divider?
   2. Does the SYSREF synchronize ALL available dividers in the chip?
   3. Does it mean that the RF phase is identical between multiple devices (synchronized by SYSREF)?

Thank you,

Zvi.