AFE7950: Latte script

David Park

Expert 6610 points

Part Number: AFE7950
Other Parts Discussed in Thread: LMK04832, ,

Hi,

Could you provide latte script for below setting?

1. Input/ouput

* DAC 1Ch

* Other all ADC and FB is disable

2. JESD204C

* Encoding : 64b/66b

* Lane late : 12.375 Gbps

* LMFSHd : 44320 (will use 2 lane)

* Input Late : 1.0 Gsps

* Resolution : 12 bits

3. Clock

* Input Clock : 187.5 MHz (Internal PLL input)

* SysRef : 5.20833 MHz (Same as FPGA)

* From LMK04832

4. NCO : 4.25 GHz

5. DAC

* 1 Ch used

* output frequency : 4.25 GHz

* Bandwidth : 1.5 GHz

Thanks.

over 1 year ago

0 Camilo Garcia Trujillo over 1 year ago

TI__Expert 5035 points

Hi David,

Could you please provide the following information about your desired mode:

Dac sample rate Fs
Bandwidth (Make sure to account for the interpolation filters that have an 80% passband. For example, to cover 1.2GHz you need 1.5GHz Bandwidth), I ask this again because you have written your input rate as 1GSPS but your Bandwidth is 1.5GHz.
Max Lane Rate supported by your FPGA

With these parameters we can make a configuration with only one DAC channel.

Best,

Camilo

0 Lee Seungky over 1 year ago

Prodigy 30 points

Hi Camilo

Dac sample rate Fs :
- 12 Gsps
Bandwidth (Make sure to account for the interpolation filters that have an 80% passband. For example, to cover 1.2GHz you need 1.5GHz Bandwidth), I ask this again because you have written your input rate as 1GSPS but your Bandwidth is 1.5GHz.
- The desired bandwidth is 1.5 GHz, but I understand that the input rate must be 1000 MHz due to the FPGA lane speed (12.5Gbps) (see JESD Formats Table below).
  
  It is believed that if the DAC interpolation is set to 12, a bandwidth of 1.5 GHz will be satisfied. Am I right?
  If it is incorrect, please set the maximum bandwidth at Input Rate 1.0 Gsps.
Max Lane Rate supported by your FPGA
- FPGA Max Lane Rate : 12.5 Gbps

Best,

seunky.lee

0 Camilo Garcia Trujillo over 1 year ago in reply to Lee Seungky

TI__Expert 5035 points

Hi Lee,

Thank you for the answer.

Just to clarify, when you have the DAC with Fs = 12GSPS and with an interpolation factor of 12, your interface rate will be 1000MSPS, but since you have to account for the interpolation filter passband of about 80%, your actual bandwidth of operation (Or maximum instantaneous bandwidth) would be 1000*0.8 = 800MHz.

With this explanation, is your bandwidth of operation 1500MHz or is that your interface rate?

If 1500MHz is your bandwidth of operation, you would need to have an interface rate of at least 1875MHz. This could be achieved by using the DAC with Fs = 12GSPS and with an interpolation factor of 6 to get an interface rate of 2000MHz, but you would need to increase the lane rate to 16.25Gbps.

If 1500MHz is your desired interface rate, you could achieve a 1200MHz bandwidth of operation by using the AFE in the following mode:

DAC Fs = 12GSPS 1 channel
Interpolation factor = 8
64b66b encoding
LMFSHd = 42220 using 4 lanes
Lane rate 12.375Gbps
16bit resolution

If this mode works please let me know and I will provide you with the configuration file.

Best,

Camilo

0 Lee Seungky over 1 year ago in reply to Camilo Garcia Trujillo

Prodigy 30 points

Hi Camilo,

Thank you for answer.

4Lane configuration is not possible because the board has already been created.

Therefore, please provide a Latte python script (Configuration file) with the following configuration.

* DAC Fs: 12 GSPS 1 Ch (Using 1TXOUT)
* Interpolation Factor: 12
* Encoding: 64b66b
* LMFSHd: 44320 Using 2 Lane (1SRX, 2SRX)
* Lane Late: 12.375 Gbps
* 12 bit resolution

Also, please provide the script (Configuration file) for the 4 Lane configuration you suggested(for future use).

Best,
Seungky.lee

0 Camilo Garcia Trujillo over 1 year ago in reply to Lee Seungky

TI__Expert 5035 points

Hi Lee,

Please see both configurations attached.

Fullscreen 64b66b_44320_12p375Gbps_12bit_TX_1000MSPS_RX_FB_disabled.py Download

##############		Read me			##############
#An external 750MHz clock, 5dBm, must be given to the LMK through J14, LMK_CLK_IN when using the AFE7950EVM

sysParams=AFE.systemParams
sysParams.__init__();sysParams.chipVersion=chipVersion

setupParams.skipFpga = 1 # setup FPGA (TSW14J56) using HSDC Pro 
##############		Top Level			##############
sysParams.FRef			= 187.5
sysParams.FadcRx		= 3000
sysParams.FadcFb		= 3000
sysParams.Fdac			= 3000*4
sysParams.externalClockRx=False
sysParams.externalClockTx=False
sysParams.RRFMode		= 5					# RRF 0: 4T4R2F FDD Mode
sysParams.enableDacInterleavedMode=False
													
##############		Digital Chain		##############

		#####	RX	#####
sysParams.rxEnable = [False,False,False,False]
sysParams.ddcFactorRx	=	[3]*4					#DDC decimation factor for RX A, B, C and D
sysParams.rxNco0		= 	[[9500,9500],			#Band0, Band1 for RXA 
							[9500,9500],        	#Band0, Band1 for RXB 
							[9500,9500],        	#Band0, Band1 for RXC 
							[9500,9500]]        	#Band0, Band1 for RXD 

		#####	FB	#####
sysParams.ddcFactorFb	=	[3]*2					#DDC decimation factor for FB 1 and 2
sysParams.fbNco0		= 	[9500,9500]				#Band0 for FB1 and FB2 
sysParams.fbEnable		=	[False,False]

		#####	TX	#####
sysParams.txEnable = [True,False,False,False]
sysParams.ducFactorTx	=	[12]*4					#DUC interpolation factor for TX A, B, C and D
sysParams.txNco0		= 	[[4250,4250],			#Band0, Band1 for TXA 
							[4250,4250],        	#Band0, Band1 for TXB 
							[4250,4250],        	#Band0, Band1 for TXC 
							[4250,4250]]        	#Band0, Band1 for TXD 
	


##############		JESD		##############

		#####	ADC-JESD	#####
sysParams.jesdSystemMode= [3,3]
													#SystemMode 0:	2R1F-FDD						; rx1-rx2-fb -fb
													#SystemMode 1:	1R1F-FDD						; rx -rx -fb -fb
													#SystemMode 2:	2R-FDD							; rx1-rx1-rx2-rx2
													#SystemMode 3:	1R								; rx -rx -rx -rx
													#SystemMode 4:	1F								; fb -fb- fb -fb
													#SystemMode 5:	1R1F-TDD						; rx/fb-rx/fb-rx/fb-rx/fb
													
sysParams.jesdTxProtocol= [2,2]						# 0 - 8b/10b encoding; 2 - 64b/66b encoding 
sysParams.LMFSHdRx		= ["44320"]*4
													# The 2nd and 4th are valid only for jesdSystemMode values in (0,2).
													# For other modes, select 4 converter modes for 1st and 3rd.
sysParams.LMFSHdFb		= ["22320","22320"]

sysParams.rxJesdTxScr	= [False,False,False,False]
sysParams.fbJesdTxScr	= [False,False]

sysParams.rxJesdTxK		= [3,3,3,3]
sysParams.fbJesdTxK		= [3,3]

sysParams.jesdTxLaneMux	= [0,1,2,3,4,5,6,7]			# Enter which lanes you want in each location. 
													# For example, if you want to exchange the first two lines of each 2T,
													#		this should be [[1,0,2,3],[5,4,6,7]]

		#####	DAC-JESD	#####
sysParams.jesdRxProtocol= [2,2]						# 0 - 8b/10b encoding; 2 - 64b/66b encoding 
sysParams.LMFSHdTx		= ["44320"]*4
sysParams.jesdRxLaneMux	= [0,1,4,5,2,3,6,7]			# Enter which lanes you want in each location.
													# For example, if you want to exchange the first two lines of each 2R
													#		this should be [[1,0,2,3],[5,4,6,7]]
sysParams.jesdRxRbd		= [4, 4]
sysParams.jesdRxScr		= [False,False,False,False]
sysParams.jesdRxK		= [3,3,3,3]
	
		#####	JESD Common	#####
	
sysParams.jesdABLvdsSync= True
sysParams.jesdCDLvdsSync= True
sysParams.syncLoopBack	= False	#JESD Sync signal is connected to FPGA

##############		GPIO		##############
sysParams.gpioMapping	= {
						'H8': 'ADC_SYNC0',
						'H7': 'ADC_SYNC1',
						'N8': 'ADC_SYNC2',
						'N7': 'ADC_SYNC3',
						'H9': 'DAC_SYNC0',
						'G9': 'DAC_SYNC1',
						'N9': 'DAC_SYNC2',
						'P9': 'DAC_SYNC3',
						'P14': 'GLOBAL_PDN',
						'K14': 'FBABTDD',
						'R6': 'FBCDTDD',
						'H15': ['TXATDD','TXBTDD'],
						'V5': ['TXCTDD','TXDTDD'],
						'E7': ['RXATDD','RXBTDD'],
						'R15': ['RXCTDD','RXDTDD']}

##############		LMK Params		##############
lmkParams.pllEn			= False
lmkParams.inputClk		= 750 # Valid only when lmkParams.pllEn = False
lmkParams.lmkFrefClk	= True
setupParams.fpgaRefClk	= 187.5 # Should be equal to LaneRate/40 for TSW14J56

##############		Logging		##############
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat=0x0
logDumpInst.rewriteFile=1
logDumpInst.rewriteFileFormat4=1
device.optimizeWrites=0
device.rawWriteLogEn=1

device.delay_time = 0
#-------------------------------------------------------------------------------------------------#
# AFE.initializeConfig()
AFE.deviceBringup()

AFE.TOP.overrideTdd(0,0,1)	# bit-wise; 4R,2F,4T

Fullscreen 64b66b_42220_12p375Gbps_16bit_TX_1500MSPS_RX_FB_disabled.py Download

##############		Read me			##############

sysParams=AFE.systemParams
sysParams.__init__();sysParams.chipVersion=chipVersion

setupParams.skipFpga = 1 # setup FPGA (TSW14J56) using HSDC Pro 
##############		Top Level			##############
sysParams.FRef			= 187.5
sysParams.FadcRx		= 3000
sysParams.FadcFb		= 3000
sysParams.Fdac			= 3000*4
sysParams.externalClockRx=False
sysParams.externalClockTx=False
sysParams.RRFMode		= 5					# RRF 0: 4T4R2F FDD Mode
sysParams.enableDacInterleavedMode=False
													
##############		Digital Chain		##############

		#####	RX	#####
sysParams.rxEnable = [False,False,False,False]
sysParams.ddcFactorRx	=	[2]*4					#DDC decimation factor for RX A, B, C and D
sysParams.rxNco0		= 	[[9500,9500],			#Band0, Band1 for RXA 
							[9500,9500],        	#Band0, Band1 for RXB 
							[9500,9500],        	#Band0, Band1 for RXC 
							[9500,9500]]        	#Band0, Band1 for RXD 

		#####	FB	#####
sysParams.ddcFactorFb	=	[2]*2					#DDC decimation factor for FB 1 and 2
sysParams.fbNco0		= 	[9500,9500]				#Band0 for FB1 and FB2 
sysParams.fbEnable		=	[False,False]

		#####	TX	#####
sysParams.txEnable = [True,False,False,False]
sysParams.ducFactorTx	=	[8]*4					#DUC interpolation factor for TX A, B, C and D
sysParams.txNco0		= 	[[4250,4250],			#Band0, Band1 for TXA 
							[4250,4250],        	#Band0, Band1 for TXB 
							[4250,4250],        	#Band0, Band1 for TXC 
							[4250,4250]]        	#Band0, Band1 for TXD 
	


##############		JESD		##############

		#####	ADC-JESD	#####
sysParams.jesdSystemMode= [3,3]
													#SystemMode 0:	2R1F-FDD						; rx1-rx2-fb -fb
													#SystemMode 1:	1R1F-FDD						; rx -rx -fb -fb
													#SystemMode 2:	2R-FDD							; rx1-rx1-rx2-rx2
													#SystemMode 3:	1R								; rx -rx -rx -rx
													#SystemMode 4:	1F								; fb -fb- fb -fb
													#SystemMode 5:	1R1F-TDD						; rx/fb-rx/fb-rx/fb-rx/fb
													
sysParams.jesdTxProtocol= [2,2]						# 0 - 8b/10b encoding; 2 - 64b/66b encoding 
sysParams.LMFSHdRx		= ["42220"]*4
													# The 2nd and 4th are valid only for jesdSystemMode values in (0,2).
													# For other modes, select 4 converter modes for 1st and 3rd.
sysParams.LMFSHdFb		= ["22210","22210"]

sysParams.rxJesdTxScr	= [False,False,False,False]
sysParams.fbJesdTxScr	= [False,False]

sysParams.rxJesdTxK		= [1,1,1,1]
sysParams.fbJesdTxK		= [1,1]

sysParams.jesdTxLaneMux	= [0,1,2,3,4,5,6,7]			# Enter which lanes you want in each location. 
													# For example, if you want to exchange the first two lines of each 2T,
													#		this should be [[1,0,2,3],[5,4,6,7]]

		#####	DAC-JESD	#####
sysParams.jesdRxProtocol= [2,2]						# 0 - 8b/10b encoding; 2 - 64b/66b encoding 
sysParams.LMFSHdTx		= ["42220"]*4
sysParams.jesdRxLaneMux	= [0,1,2,3,4,5,6,7]			# Enter which lanes you want in each location.
													# For example, if you want to exchange the first two lines of each 2R
													#		this should be [[1,0,2,3],[5,4,6,7]]
sysParams.jesdRxRbd		= [4, 4]
sysParams.jesdRxScr		= [False,False,False,False]
sysParams.jesdRxK		= [1,1,1,1]
	
		#####	JESD Common	#####
	
sysParams.jesdABLvdsSync= True
sysParams.jesdCDLvdsSync= True
sysParams.syncLoopBack	= False	#JESD Sync signal is connected to FPGA

##############		GPIO		##############
sysParams.gpioMapping	= {
						'H8': 'ADC_SYNC0',
						'H7': 'ADC_SYNC1',
						'N8': 'ADC_SYNC2',
						'N7': 'ADC_SYNC3',
						'H9': 'DAC_SYNC0',
						'G9': 'DAC_SYNC1',
						'N9': 'DAC_SYNC2',
						'P9': 'DAC_SYNC3',
						'P14': 'GLOBAL_PDN',
						'K14': 'FBABTDD',
						'R6': 'FBCDTDD',
						'H15': ['TXATDD','TXBTDD'],
						'V5': ['TXCTDD','TXDTDD'],
						'E7': ['RXATDD','RXBTDD'],
						'R15': ['RXCTDD','RXDTDD']}

##############		LMK Params		##############
lmkParams.pllEn			= False
lmkParams.inputClk		= 750 # Valid only when lmkParams.pllEn = False
lmkParams.lmkFrefClk	= True
setupParams.fpgaRefClk	= 187.5 # Should be equal to LaneRate/40 for TSW14J56

##############		Logging		##############
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat=0x0
logDumpInst.rewriteFile=1
logDumpInst.rewriteFileFormat4=1
device.optimizeWrites=0
device.rawWriteLogEn=1

device.delay_time = 0
#-------------------------------------------------------------------------------------------------#
#AFE.initializeConfig()
AFE.deviceBringup()

AFE.TOP.overrideTdd(0,0,1)	# bit-wise; 4R,2F,4T

Just a couple of comments:

If you are planning to use these configurations with the AFE7950EVM, you would need to give the AFE7950EVM a 750MHz clock so that it can generate the 187.5MHz. Because the AFE7950EVM only has a 122.88 crystal.
The enabled channel was TX1, but if you would want a different channel we can do the changes or you can just enable the desired channel and change the lane Mux accordingly.
If you are interested in phase noise performance we would suggest changing your Fref to be as close to 500MHz as possible since it will yield better phase noise out of the PLL. For this case we would just suggest changing Fref = 375MHz.

Best,

Camilo

0 Lee Seungky over 1 year ago in reply to Camilo Garcia Trujillo

Prodigy 30 points

Hi Camilo

Thank you for answer.

We are considering Dual Band to configure Bandwidth 1.5 GHz.
Is the following configuration possible in AFE7950?

* First Band:
-> Input Rate: 1000 Msps
-> LMFSHd : 44320 Using 2 Lane
-> Lane Late: 12.375 Gbps
-> Resolution: 12 bits
-> Interpolation: 12
-> DAC Fs: 12 Gsps
-> NCO: 4.7 GHz
-> output Frequency: 4.7 GHz

* Second Band
-> Input Rate: 1500 Msps
-> LMFSHd : 42220 Using 4 Lane
-> Lane Late: 12.375 Gbps
-> Resolution: 16 bits
-> Interpolation: 8
-> DAC Fs: 12 Gsps
-> NCO: 3.95 GHz
-> output Frequency: 3.95 GHz

If this dual band configuration is possible, can the two bands be combined inside the AFE7950 and output through one RF terminal (pin)?

0 Camilo Garcia Trujillo over 1 year ago in reply to Lee Seungky

TI__Expert 5035 points

Hi Lee,

This configuration would not be possible since the maximum input rate when using Dual Band mode would be 750MSPS per band and both bands must have the same input rate. For more information you can refer to table 8-6 of the AFE7950 datasheet.

Would it be possible for you to share some more details about what your end goal would be so that we can see if there is a mode that would suffice for your application? What are the characteristics (Like Max IBW)? If you would rather we could discuss this through email rather than on the forum.

Best,

Camilo

0 Camilo Garcia Trujillo over 1 year ago in reply to Camilo Garcia Trujillo

TI__Expert 5035 points

Hi Lee,

I will close this post as we have taken this to email.

Best,

Camilo

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AFE7950: Latte script