AFE7799: Rx EVM% Improvement [AL]

'''
Case			RX					TX						   FB						CLK					Notes
----	-----------------	  -----------------			-----------------			-----------			------------
2		245.76Msps, 24410     245.76Msps, 24410			245.76Msps, 12410			FS=2949.12M 
		SerDes=9830.4Mbps     SerDes=9830.4Mbps			SerDes=9830.4Mbps			REF=491.52M
		PLL0, LO=3500M		  PLL0, LO=3500M			NCO=3500M

'''
sysParams.__init__() #Resets sysParams settings to default values set in "mAfeParameters.py"
setupParams.selectedDut=1
if boardType in ("EVM","HSC1373"):
	if setupParams.selectedDut==1:
		AFE=AFE1
		device=device1
		logDumpInst=logDumpInst1
	else:
		AFE=AFE0
		device=device0
		logDumpInst=logDumpInst0
else:
	setupParams.selectedDut=0
	
sysParams=AFE.systemParams
device.hardReadAlways=False
# Consult Latte user's guide for more info on paremeters and working with config files: http://www.ti.com/lit/pdf/sbau340
##### PLL & LO
curr_lo = 4849.86
sysParams.rxAdcBw=100 #Comment out if final RX sampling rate is < 245.76MHz
sysParams.FRef                    = 491.52
sysParams.Fs                      = 2949.12
sysParams.pllMuxModes			= 0	
										#0: 4T4R Mode with PLL0 as Master. PLL 0 for all the LOs.
										#1: 4T4R Mode with PLL2 as Master. PLL 2 for all the LOs.
										#2: 4T4R FDD Mode. PLL0 for TX and PLL2 for RX.
										#3: 2*2T2R FDD Mode: PLL0 AB-TX;PLL3 AB-RX; PLL2 CD TX; PLL4 CD RX
										#4: 2T2R FDD - TDD Mode: PLL0 AB-TX; PLL3-AB-RX; PLL2 CD
sysParams.pllLo					= [curr_lo,sysParams.Fs,3501.06,1800.24,3400.0]	#PLL Frequencies for PLLs [0,1,2,3,4]
sysParams.setTxLoFbNcoFreqForTxCalib	= True #Latte sets FB NCO to TX LO value & ignores sysParams.fbNco 

## In below parameters, first in the array is for first 2T2R1F and second 2T2R1F.
# JESD and Serdes Parameters
sysParams.useSpiSysref			= False
sysParams.LMFSHdRx              = ["24410","24410"] 
sysParams.LMFSHdFb              = ["12410","12410"]
sysParams.LMFSHdTx              = ["24410","24410"]
sysParams.systemMode            = [1]*2					# 0-Identical, 1-FDD, 2-TDD
sysParams.dedicatedLaneMode     = [1]*2
sysParams.jesdProtocol          = 0#1#0				# -0:B; 1:H; 2:C
sysParams.serdesFirmware		= True
sysParams.jesdTxLaneMux			= [0,1,4,5,2,3,6,7]	# RX1...RX4 & FB1...FB2 on STX1...STX4 in shared mode. 
sysParams.jesdRxLaneMux			= [0,1,4,5,2,3,6,7]	# TX1...TX4 on SRX1...SRX4.
sysParams.jesdRxRbd				= [15, 15]
sysParams.jesdScr				= [True,True]		
sysParams.serdesTxLanePolarity	= [False,False,False,False,False,False,False,False] #This is to undo polarity inversion in AFE EVM.
sysParams.serdesRxLanePolarity	= [False,False,False,False,False,False,False,False] #This is to undo polarity inversion in AFE EVM.
sysParams.jesdK					= [32,32] 
sysParams.syncLoopBack			= False
sysParams.jesdLoopbackEn		= 0
sysParams.jesdTxRxABSyncMux		= 0 
sysParams.jesdTxRxCDSyncMux		= 0 
sysParams.jesdTxFBABSyncMux		= 0 
sysParams.jesdTxFBCDSyncMux		= 0 
sysParams.jesdRxABSyncMux		= 0 
sysParams.jesdRxCDSyncMux		= 0 
sysParams.jesdABLvdsSync		= 1
sysParams.jesdCDLvdsSync		= 1

# Decimation and interpolation Parameters
sysParams.ddcFactorRx			= [24]*2
sysParams.ddcFactorFb			= [24]*2
sysParams.ducFactorTx			= [24]*2

sysParams.fbNco					= [curr_lo,curr_lo]
sysParams.fbNcoBand1			= [curr_lo,curr_lo] #applicable only if using dual bands in FB.
sysParams.lowIfNcoRx			= [0,0] #Set a non-zero value (>=.001) if you want to enable LowIF NCO feature.
sysParams.lowIfNcoTx			= [0,0]
sysParams.lowIfNcoFb			= [0,0]
sysParams.enableFbCd			= True

LMKParams.pllEn			=	True
LMKParams.lmkFrefClk	=	True
LMKParams.sysrefFreq	=	3.84

if simulationMode==False:
	setupParams.skipFpga=0
	setupParams.skipLmk=0

# Sets GPIO to a pre-defined mode. More details can be found in https://tidrive.ext.ti.com/u/_rBkAe6wZAjssGQA/Defining_GPIO_Mapping_in_Latte.docx?l
sysParams.gpioMapping={
	'U18': u'tx_fb_loop_1',
	'T18': u'tx_fb_loop_2',
	'V18': u'tx_fb_loop_0',
	'T13': u'tdd_1f_en_ab',
	'E13': u'tdd_1f_en_cd',
	'V13': u'tdd_2r_en_ab',
	'C13': u'tdd_2r_en_cd',
	'U14': u'tdd_2t_en_ab',
	'U15': u'txiqmc_coeff_update',
	'D14': u'tdd_2t_en_cd',	
	'V5': u'adc_sync_n_ab_0',
	'V5': u'adc_sync_n_cd_0',
	'U5': u'adc_sync_n_ab_1',
	'U5': u'adc_sync_n_cd_1',
	'Y5': u'dac_sync_n_ab_0',
	'Y5': u'dac_sync_n_cd_0',
	'W5': u'dac_sync_n_ab_1',
	'W5': u'dac_sync_n_cd_1',
	'E17': u'alarm_2',
	'C17': u'alarm_1',	
	'E16': u'global_pdn',
	'D15': u'fb_nco_sw',
	'V6': u'rxa_dsa_gain_0',
	'V10': u'rxb_dsa_gain_0',
	'C6': u'rxc_dsa_gain_0',
	'D7': u'rxd_dsa_gain_0',
	}
sysParams.gpioConfigMode=3

'''
#PAP Config
sysParams.txDsaUpdateMode=1
for i in range(4):
	sysParams.srConfigParams[i]['GainStepSize']=38
	sysParams.srConfigParams[i]['AttnStepSize']=38
	sysParams.srConfigParams[i]['AmplUpdateCycles']=6
	sysParams.srConfigParams[i]['enable']=True
device.TX.DAC_DIG_AB[0].tx_top.Register52409_410h.ModeMovingAvg=2 #JPL Mode
device.TX.DAC_DIG_AB[0].tx_top.Register52409_410h.MovingAvgSamples=0 #32 samples
device.TX.DAC_DIG_AB[0].tx_top.Register52409_410h.MAWindowCntr=256
device.TX.DAC_DIG_AB[0].tx_top.Register52409_410h.MAErrorCntr=16
device.TX.DAC_DIG_AB[0].tx_top.Register52409_410h.MAAccuThresh=2560 #Triggers for a CW >-10dBFs
'''
#AGC Config
for i in range(4):
	sysParams.agcRegConfigParams[i]['enableIa']=1	#Enable Internal AGC for RX
	sysParams.agcRegConfigParams[i]['dgcEnable']=1
	sysParams.agcRegConfigParams[i]['dgcMode']=0 #IEEE Floating Point Mode after gain distribution
	sysParams.agcRegConfigParams[i]['floatingPointMode']= 0 # 0:"Don't Send MSB of Mantissa if Exp>0",1:"Send Mantissa Always"
	sysParams.agcRegConfigParams[i]['floatingPointFormat']=1 # 0:"2-bit Exp 13-bit Mantissa",1:"3-bit Exp 12 bit Mantissa",2:"4-bit Exp 11 bit Mantissa"
	sysParams.agcRegConfigParams[i]['enableEl']=0
	
	sysParams.agcRegConfigParams[i]['thresholdSa']=-3
	sysParams.agcRegConfigParams[i]['windowLenSa']=256
	sysParams.agcRegConfigParams[i]['stepSizeSa']=1
	sysParams.agcRegConfigParams[i]['numHitsSa']=32
	sysParams.agcRegConfigParams[i]['enableSa']=1
	
	sysParams.agcRegConfigParams[i]['thresholdSd']=-7
	sysParams.agcRegConfigParams[i]['windowLenSd']=512
	sysParams.agcRegConfigParams[i]['stepSizeSd']=1
	sysParams.agcRegConfigParams[i]['numHitsSd']=32
	sysParams.agcRegConfigParams[i]['enableSd']=1
	
	sysParams.agcRegConfigParams[i]['thresholdBa']=-2
	sysParams.agcRegConfigParams[i]['windowLenBa']=128
	sysParams.agcRegConfigParams[i]['stepSizeBa']=3
	sysParams.agcRegConfigParams[i]['numHitsBa']=32
	sysParams.agcRegConfigParams[i]['enableBa']=1
	
	sysParams.agcRegConfigParams[i]['thresholdBd']=-6
	sysParams.agcRegConfigParams[i]['windowLenBd']=256
	sysParams.agcRegConfigParams[i]['stepSizeBd']=3
	sysParams.agcRegConfigParams[i]['numHitsBd']=32
	sysParams.agcRegConfigParams[i]['enableBd']=1
'''
#INT Pins
sysParams.intPinsParams[0]['JESD']=True
sysParams.intPinsParams[0]['SPI']=True
sysParams.intPinsParams[0]['SRTXA']=True
sysParams.intPinsParams[0]['SRTXB']=True
sysParams.intPinsParams[0]['SRTXC']=True
sysParams.intPinsParams[0]['SRTXD']=True
sysParams.intPinsParams[0]['PLL0']=True
sysParams.intPinsParams[0]['PLL1']=True
sysParams.intPinsParams[0]['PLL2']=True
sysParams.intPinsParams[0]['PLL3']=True
sysParams.intPinsParams[0]['PLL4']=True
'''

#Calibrations
sysParams.enableRxDsaFactoryCal 	  = False
sysParams.enableTxDsaFactoryCal 	  = False
sysParams.enableTxIqmcLolTrackingCorr = True
sysParams.enableRxIqmcLolTrackingCorr = True
sysParams.txIqMcCalibMode			  = 2		# 0 -Single Fb Mode FB AB ; 1 -Single Fb Mode FB CD ; 2- Dual Fb_Mode
sysParams.txDsaCalibMode			  = 0
sysParams.rxDsaCalibMode			  = 0
sysParams.txIqmcFullBandEstimation	  = False

logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"Case-2_Comba_20220121.txt")
logDumpInst.logFormat=0x4
logDumpInst.rewriteFile=1


logDumpInst.enableReadCheck=True
logDumpInst.enableReads= False
device.rawWriteLogEn=1
device.rewriteFile=1

lmk.rawWriteLogEn=0

# AFE.initializeConfig()
AFE.deviceBringup()

device.rawWriteLogEn=1
lmk.rawWriteLogEn=0

engine.sampleNo=32768

AFE.TOP.overrideTdd(1, 1, 1) # (RX, FB, TX) forcing TDD TDD state through SPI. 1=enable;0=disable

def synch(val):
	device.JESD.ADC_TX[0].ADC_TX.JESD_TX_CONFIG83.sync_override=12
	device.JESD.ADC_TX[0].ADC_TX.JESD_TX_CONFIG83.sync=12*val
	device.JESD.ADC_TX[1].ADC_TX.JESD_TX_CONFIG83.sync_override=12
	device.JESD.ADC_TX[1].ADC_TX.JESD_TX_CONFIG83.sync=12*val


device.hardReadAlways=True
device.currentPageSelected.setValue(0)
device.logEn=1

device.JESD.SUBCHIP.SUBCHIP.JESD_SUBCHIP_REG72.loop_back_mode_tx1=1 # 0
device.JESD.SUBCHIP.SUBCHIP.JESD_SUBCHIP_REG72.loop_back_mode_tx0=1
device.JESD.SUBCHIP.SUBCHIP.JESD_SUBCHIP_REG73.serdes_fifo_read_dly=1
device.JESD.SUBCHIP.SUBCHIP.JESD_SUBCHIP_REG73.loop_back_fifo_init_state=1
device.JESD.SUBCHIP.SUBCHIP.JESD_SUBCHIP_REG73.loop_back_fifo_init_state=0

for chNo in range(2):
	for offset in range(4):
		device.JESD.SERDES[chNo].laneRegisters[offset].TIMING_PHASE12_OVERWRITE.OWEN_PHASE1_ACC=1

synch(1)
synch(0)
device.currentPageSelected.setValue(0)
device.logEn=0
AFE.JESDRX[0].getJesdAlarms(1)
AFE.JESDRX[1].getJesdAlarms(1)

device.currentPageSelected.setValue(0)



#raise

# change lane mux
sysParams.jesdTxLaneMux			= [0,1,2,3,4,5,6,7]	
AFE.JESD.SUBCHIP.configJesdTxLaneMux(sysParams.jesdTxLaneMux)
sysParams.jesdRxLaneMux			= [0,1,2,3,4,5,6,7]	
AFE.JESD.SUBCHIP.configJesdRxLaneMux(sysParams.jesdRxLaneMux)



device.currentPageSelected.setValue(0)

# changing lane mux
device.writeReg(0x15,0x08)
device.writeReg(0xC4,0x10)
device.writeReg(0xC4,0x10)
device.writeReg(0xC5,0x32)
device.writeReg(0xC5,0x32)
device.writeReg(0xC6,0x54)
device.writeReg(0xC6,0x54)
device.writeReg(0xC7,0x76)
device.writeReg(0xC7,0x76)
device.writeReg(0xC8,0x10)
device.writeReg(0xC8,0x10)
device.writeReg(0xC9,0x32)
device.writeReg(0xC9,0x32)
device.writeReg(0xCA,0x54)
device.writeReg(0xCA,0x54)
device.writeReg(0xCB,0x76)
device.writeReg(0xCB,0x76)
device.writeReg(0xCC,0x10)
device.writeReg(0xCC,0x10)
device.writeReg(0xCD,0x32)
device.writeReg(0xCD,0x32)
device.writeReg(0xCE,0x54)
device.writeReg(0xCE,0x54)
device.writeReg(0xCF,0x76)
device.writeReg(0xCF,0x76)
device.writeReg(0xD0,0x10)
device.writeReg(0xD0,0x10)
device.writeReg(0xD1,0x32)
device.writeReg(0xD1,0x32)
device.writeReg(0xD2,0x54)
device.writeReg(0xD2,0x54)
device.writeReg(0xD3,0x76)
device.writeReg(0xD3,0x76)
device.writeReg(0x15,0x00)

# enable FB to TX JESD loopback
device.writeReg(0x15,0x08)
device.writeReg(0x48,0x05)
device.writeReg(0x48,0x05)
device.writeReg(0x49,0x02)
device.writeReg(0x49,0x03)
device.writeReg(0x49,0x02)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x04)
device.writeReg(0x15,0x04)
device.writeReg(0x4687,0x80)
device.writeReg(0x4686,0x00)
device.writeReg(0x4487,0x80)
device.writeReg(0x4486,0x00)
device.writeReg(0x4087,0x80)
device.writeReg(0x4086,0x00)
device.writeReg(0x4287,0x80)
device.writeReg(0x4286,0x00)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x40)
device.writeReg(0x4287,0x80)
device.writeReg(0x4286,0x00)
device.writeReg(0x4087,0x80)
device.writeReg(0x4086,0x00)
device.writeReg(0x4487,0x80)
device.writeReg(0x4486,0x00)
device.writeReg(0x4687,0x80)
device.writeReg(0x4686,0x00)
device.writeReg(0x15,0x40)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x01)
device.writeReg(0x15,0x01)
device.writeReg(0x72,0xC0)
device.writeReg(0x72,0xCC)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x10)
device.writeReg(0x72,0xC0)
device.writeReg(0x72,0xCC)
device.writeReg(0x15,0x11)
device.writeReg(0x15,0x01)
device.writeReg(0x72,0xCC)
device.writeReg(0x72,0xC0)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x10)
device.writeReg(0x72,0xCC)
device.writeReg(0x72,0xC0)
device.writeReg(0x15,0x10)
device.writeReg(0x15,0x00)

# read alarms
device.writeReg(0x15,0x02)
device.writeReg(0x81,0xFF)
device.writeReg(0x81,0x00)
device.writeReg(0x2D,0xDB)
device.writeReg(0x2D,0x9B)
device.writeReg(0x190,0x01)
device.writeReg(0x190,0x00)
device.writeReg(0x190,0x04)
device.writeReg(0x190,0x00)
device.readReg(0x00000163)
device.readReg(0x00000162)
device.readReg(0x00000161)
device.readReg(0x00000160)
device.readReg(0x00000167)
device.readReg(0x00000166)
device.readReg(0x00000165)
device.readReg(0x00000164)
device.readReg(0x0000012A) # expected 0xa
device.readReg(0x0000012C) # expected 0x5
device.writeReg(0x15,0x20)
device.writeReg(0x81,0xFF)
device.writeReg(0x81,0x00)
device.writeReg(0x2D,0xDB)
device.writeReg(0x2D,0x9B)
device.writeReg(0x190,0x01)
device.writeReg(0x190,0x00)
device.writeReg(0x190,0x04)
device.writeReg(0x190,0x00)
device.readReg(0x00000163)
device.readReg(0x00000162)
device.readReg(0x00000161)
device.readReg(0x00000160)
device.readReg(0x00000167)
device.readReg(0x00000166)
device.readReg(0x00000165)
device.readReg(0x00000164)
device.readReg(0x0000012A) # expected 0xa
device.readReg(0x0000012C) # expected 0x5
device.writeReg(0x15,0x00)

\\START: Overriding TDD Pins internally for Rx,Fb,Tx enable

SPIWrite 0124,01,0,7	//Property44708_0_0=0x1; 	Address(0x124[0:0],)
SPIWrite 0126,01,0,7	//Property44709_16_16=0x1; 	Address(0x124[16:16],)
SPIWrite 0128,01,0,7	//Property44710_0_0=0x1; 	Address(0x128[0:0],)
SPIWrite 012a,01,0,7	//Property44711_16_16=0x1; 	Address(0x128[16:16],)
SPIWrite 012c,01,0,7	//Property44712_0_0=0x1; 	Address(0x12c[0:0],)
SPIWrite 012e,01,0,7	//Property44713_16_16=0x1; 	Address(0x12c[16:16],)
SPIWrite 0125,01,0,7	//Property44714_8_8=0x1; 	Address(0x124[8:8],)
SPIWrite 0127,01,0,7	//Property44715_24_24=0x1; 	Address(0x124[24:24],)
SPIWrite 0129,00,0,7	//Property44716_8_8=0x0; 	Address(0x128[8:8],)
SPIWrite 012b,01,0,7	//Property44717_24_24=0x1; 	Address(0x128[24:24],)
SPIWrite 012d,01,0,7	//Property44718_8_8=0x1; 	Address(0x12c[8:8],)
SPIWrite 012f,00,0,7	//Property44719_24_24=0x0; 	Address(0x12c[24:24],)

\\END: Done overriding TDD Pins internally

SPIWrite 0014,00,2,2	//PAGE: TIMING_CON=0x0;(Meaning: ); 	Address(0x14[2:2],)
SPIWrite 0015,08,3,3	//PAGE: jesd_subchip=0x1;(Meaning: ); 	Address(0x15[3:3],)
SPIWrite 0048,04,2,3
SPIWrite 0048,05,0,1
SPIWrite 0049,03,1,4
SPIWrite 0049,03,0,0
SPIWrite 0049,02,0,0
SPIWrite 0015,00,3,3	//PAGE: jesd_subchip=0x0;(Meaning: ); 	Address(0x15[3:3],)
SPIWrite 0015,04,2,2	//PAGE: SERDES=0x1; 	Address(0x15[2:2],0x15[6:6],)
SPIWrite 0015,04,6,6
SPIWrite 0015,00,2,2	//PAGE: SERDES=0x0; 	Address(0x15[2:2],0x15[6:6],)
SPIWrite 0015,00,6,6
SPIWrite 0015,08,3,3	//PAGE: jesd_subchip=0x1;(Meaning: ); 	Address(0x15[3:3],)

\\Read	serdesab_apb_page_addr_index=0x2;(Meaning: ); 	Address(0x20[9:8],)

SPIWrite 4687,80,0,7	//OWEN_PHASE1_ACC=0x1; 	Address(0x8043[15:15],)
SPIWrite 4686,00,0,7
SPIWrite 0015,00,3,3	//PAGE: jesd_subchip=0x0;(Meaning: ); 	Address(0x15[3:3],)
SPIWrite 0015,04,2,2	//PAGE: SERDES=0x1; 	Address(0x15[2:2],0x15[6:6],)
SPIWrite 0015,04,6,6
SPIWrite 0015,00,2,2	//PAGE: SERDES=0x0; 	Address(0x15[2:2],0x15[6:6],)
SPIWrite 0015,00,6,6
SPIWrite 0015,08,3,3	//PAGE: jesd_subchip=0x1;(Meaning: ); 	Address(0x15[3:3],)

\\Read	serdesab_apb_page_addr_index=0x2;(Meaning: ); 	Address(0x20[9:8],)

SPIWrite 4487,80,0,7	//OWEN_PHASE1_ACC=0x1; 	Address(0x8043[15:15],)
SPIWrite 4486,00,0,7
SPIWrite 0015,00,3,3	//PAGE: jesd_subchip=0x0;(Meaning: ); 	Address(0x15[3:3],)
SPIWrite 0015,04,2,2	//PAGE: SERDES=0x1; 	Address(0x15[2:2],0x15[6:6],)
SPIWrite 0015,04,6,6
SPIWrite 0015,00,2,2	//PAGE: SERDES=0x0; 	Address(0x15[2:2],0x15[6:6],)
SPIWrite 0015,00,6,6
SPIWrite 0015,08,3,3	//PAGE: jesd_subchip=0x1;(Meaning: ); 	Address(0x15[3:3],)

\\Read	serdesab_apb_page_addr_index=0x2;(Meaning: ); 	Address(0x20[9:8],)

SPIWrite 4087,80,0,7	//OWEN_PHASE1_ACC=0x1; 	Address(0x8043[15:15],)
SPIWrite 4086,00,0,7
SPIWrite 0015,00,3,3	//PAGE: jesd_subchip=0x0;(Meaning: ); 	Address(0x15[3:3],)
SPIWrite 0015,04,2,2	//PAGE: SERDES=0x1; 	Address(0x15[2:2],0x15[6:6],)
SPIWrite 0015,04,6,6
SPIWrite 0015,00,2,2	//PAGE: SERDES=0x0; 	Address(0x15[2:2],0x15[6:6],)
SPIWrite 0015,00,6,6
SPIWrite 0015,08,3,3	//PAGE: jesd_subchip=0x1;(Meaning: ); 	Address(0x15[3:3],)

\\Read	serdesab_apb_page_addr_index=0x2;(Meaning: ); 	Address(0x20[9:8],)

SPIWrite 4287,80,0,7	//OWEN_PHASE1_ACC=0x1; 	Address(0x8043[15:15],)
SPIWrite 4286,00,0,7
SPIWrite 0015,00,3,3	//PAGE: jesd_subchip=0x0;(Meaning: ); 	Address(0x15[3:3],)
SPIWrite 0015,00,2,2	//PAGE: SERDES=0x2; 	Address(0x15[2:2],0x15[6:6],)
SPIWrite 0015,40,6,6
SPIWrite 0015,40,2,2	//PAGE: SERDES=0x0; 	Address(0x15[2:2],0x15[6:6],)
SPIWrite 0015,00,6,6
SPIWrite 0015,08,3,3	//PAGE: jesd_subchip=0x1;(Meaning: ); 	Address(0x15[3:3],)

\\Read	serdescd_apb_page_addr_index=0x2;(Meaning: ); 	Address(0x20[17:16],)

SPIWrite 4287,80,0,7	//OWEN_PHASE1_ACC=0x1; 	Address(0x8043[15:15],)
SPIWrite 4286,00,0,7
SPIWrite 0015,00,3,3	//PAGE: jesd_subchip=0x0;(Meaning: ); 	Address(0x15[3:3],)
SPIWrite 0015,00,2,2	//PAGE: SERDES=0x2; 	Address(0x15[2:2],0x15[6:6],)
SPIWrite 0015,40,6,6
SPIWrite 0015,40,2,2	//PAGE: SERDES=0x0; 	Address(0x15[2:2],0x15[6:6],)
SPIWrite 0015,00,6,6
SPIWrite 0015,08,3,3	//PAGE: jesd_subchip=0x1;(Meaning: ); 	Address(0x15[3:3],)

\\Read	serdescd_apb_page_addr_index=0x2;(Meaning: ); 	Address(0x20[17:16],)

SPIWrite 4087,80,0,7	//OWEN_PHASE1_ACC=0x1; 	Address(0x8043[15:15],)
SPIWrite 4086,00,0,7
SPIWrite 0015,00,3,3	//PAGE: jesd_subchip=0x0;(Meaning: ); 	Address(0x15[3:3],)
SPIWrite 0015,00,2,2	//PAGE: SERDES=0x2; 	Address(0x15[2:2],0x15[6:6],)
SPIWrite 0015,40,6,6
SPIWrite 0015,40,2,2	//PAGE: SERDES=0x0; 	Address(0x15[2:2],0x15[6:6],)
SPIWrite 0015,00,6,6
SPIWrite 0015,08,3,3	//PAGE: jesd_subchip=0x1;(Meaning: ); 	Address(0x15[3:3],)

\\Read	serdescd_apb_page_addr_index=0x2;(Meaning: ); 	Address(0x20[17:16],)

SPIWrite 4487,80,0,7	//OWEN_PHASE1_ACC=0x1; 	Address(0x8043[15:15],)
SPIWrite 4486,00,0,7
SPIWrite 0015,00,3,3	//PAGE: jesd_subchip=0x0;(Meaning: ); 	Address(0x15[3:3],)
SPIWrite 0015,00,2,2	//PAGE: SERDES=0x2; 	Address(0x15[2:2],0x15[6:6],)
SPIWrite 0015,40,6,6
SPIWrite 0015,40,2,2	//PAGE: SERDES=0x0; 	Address(0x15[2:2],0x15[6:6],)
SPIWrite 0015,00,6,6
SPIWrite 0015,08,3,3	//PAGE: jesd_subchip=0x1;(Meaning: ); 	Address(0x15[3:3],)

\\Read	serdescd_apb_page_addr_index=0x2;(Meaning: ); 	Address(0x20[17:16],)

SPIWrite 4687,80,0,7	//OWEN_PHASE1_ACC=0x1; 	Address(0x8043[15:15],)
SPIWrite 4686,00,0,7
SPIWrite 0015,00,3,3	//PAGE: jesd_subchip=0x0;(Meaning: ); 	Address(0x15[3:3],)
SPIWrite 0015,01,0,0	//PAGE: rx_jesd=0x1; 	Address(0x15[0:0],0x15[4:4],)
SPIWrite 0015,01,4,4
SPIWrite 0072,c0,4,7	//sync_override=0xc; 	Address(0x70[23:20],)
SPIWrite 0072,cc,0,3	//sync=0xc; 	Address(0x70[19:16],)
SPIWrite 0015,00,0,0	//PAGE: rx_jesd=0x2; 	Address(0x15[0:0],0x15[4:4],)
SPIWrite 0015,10,4,4
SPIWrite 0072,c0,4,7	//sync_override=0xc; 	Address(0x70[23:20],)
SPIWrite 0072,cc,0,3	//sync=0xc; 	Address(0x70[19:16],)
SPIWrite 0015,11,0,0	//PAGE: rx_jesd=0x1; 	Address(0x15[0:0],0x15[4:4],)
SPIWrite 0015,01,4,4
SPIWrite 0072,cc,4,7	//sync_override=0xc; 	Address(0x70[23:20],)
SPIWrite 0072,c0,0,3	//sync=0x0; 	Address(0x70[19:16],)
SPIWrite 0015,00,0,0	//PAGE: rx_jesd=0x2; 	Address(0x15[0:0],0x15[4:4],)
SPIWrite 0015,10,4,4
SPIWrite 0072,cc,4,7	//sync_override=0xc; 	Address(0x70[23:20],)
SPIWrite 0072,c0,0,3	//sync=0x0; 	Address(0x70[19:16],)
SPIWrite 0015,10,0,0	//PAGE: rx_jesd=0x0; 	Address(0x15[0:0],0x15[4:4],)
SPIWrite 0015,00,4,4

\\START: Reading the JESD RX states to check if link is established


\\START: Clearing JESD RX Data and alarms

SPIWrite 0015,02,1,1	//PAGE: tx_jesd=0x1; 	Address(0x15[1:1],0x15[5:5],)
SPIWrite 0015,02,5,5
SPIWrite 0081,ff,0,7	//jesd_clear_data=0xff; 	Address(0x80[15:8],)
SPIWrite 0081,00,0,7	//jesd_clear_data=0x0; 	Address(0x80[15:8],)
SPIWrite 002d,db,6,6	//serdes_fifo_err_clear=0x1; 	Address(0x2c[14:14],)
SPIWrite 002d,9b,6,6	//serdes_fifo_err_clear=0x0; 	Address(0x2c[14:14],)
SPIWrite 0190,01,0,0	//clear_all_alarms=0x1; 	Address(0x190[0:0],)
SPIWrite 0190,00,0,0	//clear_all_alarms=0x0; 	Address(0x190[0:0],)
SPIWrite 0190,04,2,2	//clear_all_alarms_to_pap=0x1; 	Address(0x190[2:2],)
SPIWrite 0190,00,2,2	//clear_all_alarms_to_pap=0x0; 	Address(0x190[2:2],)

\\END: Done clearing JESD RX Data and alarms


WAIT 0.001

SPIReadCheck 0163,0,7,00
SPIReadCheck 0162,0,7,00
SPIReadCheck 0161,0,7,00
SPIReadCheck 0160,0,7,00
SPIReadCheck 0167,0,7,00
SPIReadCheck 0166,0,7,00
SPIReadCheck 0165,0,7,00
SPIReadCheck 0164,0,7,00

\\Read	alarms=0x0; 	Address(0x160[31:0],0x164[31:0],)

SPIReadCheck 0135,4,4,10

\\Read	comma_align_lock_lane0_monitor_flag=0x1; 	Address(0x134[12:12],)

SPIReadCheck 0135,5,5,20

\\Read	comma_align_lock_lane1_monitor_flag=0x1; 	Address(0x134[13:13],)

SPIReadCheck 012a,0,7,0a

\\Read	jesd_cs_state_tx0=0xa; 	Address(0x128[23:16],)

SPIReadCheck 012c,0,7,05

\\Read	jesd_fs_state_tx0=0x5; 	Address(0x12c[7:0],)


\\END: Done reading the JESD RX states to check if link is established


\\START: Reading the JESD RX states to check if link is established


\\START: Clearing JESD RX Data and alarms

SPIWrite 0015,00,1,1	//PAGE: tx_jesd=0x2; 	Address(0x15[1:1],0x15[5:5],)
SPIWrite 0015,20,5,5
SPIWrite 0081,ff,0,7	//jesd_clear_data=0xff; 	Address(0x80[15:8],)
SPIWrite 0081,00,0,7	//jesd_clear_data=0x0; 	Address(0x80[15:8],)
SPIWrite 002d,db,6,6	//serdes_fifo_err_clear=0x1; 	Address(0x2c[14:14],)
SPIWrite 002d,9b,6,6	//serdes_fifo_err_clear=0x0; 	Address(0x2c[14:14],)
SPIWrite 0190,01,0,0	//clear_all_alarms=0x1; 	Address(0x190[0:0],)
SPIWrite 0190,00,0,0	//clear_all_alarms=0x0; 	Address(0x190[0:0],)
SPIWrite 0190,04,2,2	//clear_all_alarms_to_pap=0x1; 	Address(0x190[2:2],)
SPIWrite 0190,00,2,2	//clear_all_alarms_to_pap=0x0; 	Address(0x190[2:2],)

\\END: Done clearing JESD RX Data and alarms


WAIT 0.001

SPIReadCheck 0163,0,7,00
SPIReadCheck 0162,0,7,00
SPIReadCheck 0161,0,7,00
SPIReadCheck 0160,0,7,00
SPIReadCheck 0167,0,7,00
SPIReadCheck 0166,0,7,00
SPIReadCheck 0165,0,7,00
SPIReadCheck 0164,0,7,00

\\Read	alarms=0x0; 	Address(0x160[31:0],0x164[31:0],)

SPIReadCheck 0135,4,4,10

\\Read	comma_align_lock_lane0_monitor_flag=0x1; 	Address(0x134[12:12],)

SPIReadCheck 0135,5,5,20

\\Read	comma_align_lock_lane1_monitor_flag=0x1; 	Address(0x134[13:13],)

SPIReadCheck 012a,0,7,0a

\\Read	jesd_cs_state_tx0=0xa; 	Address(0x128[23:16],)

SPIReadCheck 012c,0,7,05

\\Read	jesd_fs_state_tx0=0x5; 	Address(0x12c[7:0],)


\\END: Done reading the JESD RX states to check if link is established

SPIWrite 0015,20,1,1	//PAGE: tx_jesd=0x0; 	Address(0x15[1:1],0x15[5:5],)
SPIWrite 0015,00,5,5

\\START: Configuring JESD TX Lane Mux

SPIWrite 0015,08,3,3	//PAGE: jesd_subchip=0x1;(Meaning: ); 	Address(0x15[3:3],)
SPIWrite 004a,10,0,2
SPIWrite 004a,10,4,6
SPIWrite 004b,52,0,2
SPIWrite 004b,32,4,6
SPIWrite 004c,34,0,2
SPIWrite 004c,54,4,6
SPIWrite 004d,76,0,2
SPIWrite 004d,76,4,6
SPIWrite 004e,10,0,2
SPIWrite 004e,10,4,6
SPIWrite 004f,52,0,2
SPIWrite 004f,32,4,6
SPIWrite 0050,34,0,2
SPIWrite 0050,54,4,6
SPIWrite 0051,76,0,2
SPIWrite 0051,76,4,6

\\END: Done configuring JESD TX Lane Mux


\\START: Configuring JESD RX Lane Mux

SPIWrite 0068,10,0,2
SPIWrite 0068,10,4,6
SPIWrite 0069,52,0,2
SPIWrite 0069,32,4,6
SPIWrite 006a,34,0,2
SPIWrite 006a,54,4,6
SPIWrite 006b,76,0,2
SPIWrite 006b,76,4,6
SPIWrite 006c,10,0,2
SPIWrite 006c,10,4,6
SPIWrite 006d,52,0,2
SPIWrite 006d,32,4,6
SPIWrite 006e,34,0,2
SPIWrite 006e,54,4,6
SPIWrite 006f,76,0,2
SPIWrite 006f,76,4,6

\\END: Done configuring JESD RX Lane Mux

SPIWrite 0015,00,3,3	//PAGE: jesd_subchip=0x0;(Meaning: ); 	Address(0x15[3:3],)
SPIWrite 0015,08,0,7
SPIWrite 00c4,10,0,7
SPIWrite 00c4,10,0,7
SPIWrite 00c5,32,0,7
SPIWrite 00c5,32,0,7
SPIWrite 00c6,54,0,7
SPIWrite 00c6,54,0,7
SPIWrite 00c7,76,0,7
SPIWrite 00c7,76,0,7
SPIWrite 00c8,10,0,7
SPIWrite 00c8,10,0,7
SPIWrite 00c9,32,0,7
SPIWrite 00c9,32,0,7
SPIWrite 00ca,54,0,7
SPIWrite 00ca,54,0,7
SPIWrite 00cb,76,0,7
SPIWrite 00cb,76,0,7
SPIWrite 00cc,10,0,7
SPIWrite 00cc,10,0,7
SPIWrite 00cd,32,0,7
SPIWrite 00cd,32,0,7
SPIWrite 00ce,54,0,7
SPIWrite 00ce,54,0,7
SPIWrite 00cf,76,0,7
SPIWrite 00cf,76,0,7
SPIWrite 00d0,10,0,7
SPIWrite 00d0,10,0,7
SPIWrite 00d1,32,0,7
SPIWrite 00d1,32,0,7
SPIWrite 00d2,54,0,7
SPIWrite 00d2,54,0,7
SPIWrite 00d3,76,0,7
SPIWrite 00d3,76,0,7
SPIWrite 0015,00,0,7
SPIWrite 0015,08,0,7
SPIWrite 0048,05,0,7
SPIWrite 0048,05,0,7
SPIWrite 0049,02,0,7
SPIWrite 0049,03,0,7
SPIWrite 0049,02,0,7
SPIWrite 0015,00,0,7
SPIWrite 0015,04,0,7
SPIWrite 0015,04,0,7
SPIWrite 4687,80,0,7
SPIWrite 4686,00,0,7
SPIWrite 4487,80,0,7
SPIWrite 4486,00,0,7
SPIWrite 4087,80,0,7
SPIWrite 4086,00,0,7
SPIWrite 4287,80,0,7
SPIWrite 4286,00,0,7
SPIWrite 0015,00,0,7
SPIWrite 0015,40,0,7
SPIWrite 4287,80,0,7
SPIWrite 4286,00,0,7
SPIWrite 4087,80,0,7
SPIWrite 4086,00,0,7
SPIWrite 4487,80,0,7
SPIWrite 4486,00,0,7
SPIWrite 4687,80,0,7
SPIWrite 4686,00,0,7
SPIWrite 0015,40,0,7
SPIWrite 0015,00,0,7
SPIWrite 0015,01,0,7
SPIWrite 0015,01,0,7
SPIWrite 0072,c0,0,7
SPIWrite 0072,cc,0,7
SPIWrite 0015,00,0,7
SPIWrite 0015,10,0,7
SPIWrite 0072,c0,0,7
SPIWrite 0072,cc,0,7
SPIWrite 0015,11,0,7
SPIWrite 0015,01,0,7
SPIWrite 0072,cc,0,7
SPIWrite 0072,c0,0,7
SPIWrite 0015,00,0,7
SPIWrite 0015,10,0,7
SPIWrite 0072,cc,0,7
SPIWrite 0072,c0,0,7
SPIWrite 0015,10,0,7
SPIWrite 0015,00,0,7
SPIWrite 0015,02,0,7
SPIWrite 0081,ff,0,7
SPIWrite 0081,00,0,7
SPIWrite 002d,db,0,7
SPIWrite 002d,9b,0,7
SPIWrite 0190,01,0,7
SPIWrite 0190,00,0,7
SPIWrite 0190,04,0,7
SPIWrite 0190,00,0,7
SPIWrite 0015,20,0,7
SPIWrite 0081,ff,0,7
SPIWrite 0081,00,0,7
SPIWrite 002d,db,0,7
SPIWrite 002d,9b,0,7
SPIWrite 0190,01,0,7
SPIWrite 0190,00,0,7
SPIWrite 0190,04,0,7
SPIWrite 0190,00,0,7
SPIWrite 0015,00,0,7

from mDevice import Device
from HSCEngines import HSCEngineWithILDDCDGC
from HSCProcesses import HSCProcessWithILDDCDGC
from mConnect import Connect

import mCPLD_Device
reload(mCPLD_Device)
import sys
import mAnupam_PG1
reload(mAnupam_PG1)
from mAnupam_PG1 import ANUPAM
import mlmkDevice
reload(mlmkDevice)
import globalDefs as Globals

if boardType in ("BENCH","HSC1330"):# or simulationMode==True:
	if simulationMode==False:
		adcregProg.addressLen=16
		adcregProg.packetLen=24
		adcregProg.packetOrder=0
		adcregProg.msbFirst=1
		adcregProg.clkEdge=1
		if boardType in ("BENCH",):
			adcregProg.pin0=5#0#
			adcregProg.pin1=5#1#
			adcregProg.pin2=5#6#
			adcregProg.pin3=5#2#
			adcregProg.pin4=0#5#
			adcregProg.pin5=1#5#
			adcregProg.pin6=6#5#
			adcregProg.pin7=2#5#
		else:
			adcregProg.pin0=0#
			adcregProg.pin1=1#
			adcregProg.pin2=6#
			adcregProg.pin3=2#
			adcregProg.pin4=5#
			adcregProg.pin5=5#
			adcregProg.pin6=5#
			adcregProg.pin7=3#
			boardType="BENCH"
		adcregProg.readClkEdge=1
		
		if jesdH==True:
			fpgaregProg.addressLen=16
			fpgaregProg.packetLen=24
			fpgaregProg.packetOrder=0
			fpgaregProg.msbFirst=1
			fpgaregProg.clkEdge=1
			fpgaregProg.pin0=5
			fpgaregProg.pin1=1
			fpgaregProg.pin2=2
			fpgaregProg.pin3=0
			fpgaregProg.pin4=6
			fpgaregProg.pin5=5
			fpgaregProg.pin6=5
			fpgaregProg.pin7=5
		else:			
			fpgaregProg.addressLen=7
			fpgaregProg.packetLen=39
			fpgaregProg.packetOrder=0
			fpgaregProg.msbFirst=1
			fpgaregProg.clkEdge=1
			fpgaregProg.pin0=5
			fpgaregProg.pin1=0
			fpgaregProg.pin2=6
			fpgaregProg.pin3=2
			fpgaregProg.pin4=3
			fpgaregProg.pin5=5
			fpgaregProg.pin6=5
			fpgaregProg.pin7=1
		
		lmkregProg.addressLen=16
		lmkregProg.packetLen=24
		lmkregProg.packetOrder=0
		lmkregProg.msbFirst=1
		lmkregProg.clkEdge=1
		lmkregProg.pin0=5
		lmkregProg.pin1=5
		lmkregProg.pin2=5
		lmkregProg.pin3=5
		lmkregProg.pin4=3
		lmkregProg.pin5=2
		lmkregProg.pin6=0
		lmkregProg.pin7=1
		
		gpioProg.pin0=3
		gpioProg.pin1=3
		gpioProg.pin2=3
		gpioProg.pin3=3
		gpioProg.pin4=3
		gpioProg.pin5=3
		gpioProg.pin6=3
		gpioProg.pin7=3
		
		jtagregProg.pin0=5
		jtagregProg.pin1=5
		jtagregProg.pin2=5
		jtagregProg.pin3=5
		jtagregProg.pin4=5
		jtagregProg.pin5=5
		jtagregProg.pin6=5
		jtagregProg.pin7=5
		
	device=ANUPAM(fileName=Globals.libFolderPath+"//"+"resourceFiles//"+Afe77xxLibraries.folderDirDict[folderName]['dmlName'],regProgDevice=adcregProg,name='DONOT_OPEN_'+Afe77xxLibraries.folderDirDict[folderName]['dmlName'][:-4]+'_FULL')
	if jesdH==True:
		from JESD204H import JESD204H
		myfpga=JESD204H(name="JESD204H_FPGA",fileName=Globals.libFolderPath+"\\resourceFiles\\JESD204H.dml", regProgDevice=fpgaregProg,captureDevice=capDev)
		info("Loading JESD 204H FPGA DML")
	else:
		import ANUPAM_FPGA
		reload(ANUPAM_FPGA)
		myfpga=ANUPAM_FPGA.ANUPAM_FPGA(regProgDevice=fpgaregProg,fileName=Globals.libFolderPath+"\\resourceFiles\\AFE77xx_FPGA.dml",captureDevice=capDev)
		myfpga.setResetProperty(myfpga.head.page.Common.Reset._Reset_all)
		info("Loading JESD 204B FPGA DML")

elif boardType=='HSC1320':
	if simulationMode==False:
		dut0_spia.addressLen=16
		dut0_spia.packetLen = 24
		dut0_spia.pin0 = 0
		dut0_spia.pin1 = 1 
		dut0_spia.pin2 = 5
		dut0_spia.pin3 = 5
		dut0_spia.pin4 = 6
		dut0_spia.pin5 = 2
		dut0_spia.pin6 = 5
		dut0_spia.pin7 = 5
		dut0_spia.clkEdge=1
		dut0_spia.msbFirst = 1
		
		dut1_spia.addressLen=16
		dut1_spia.packetLen = 24
		dut1_spia.pin0 = 0
		dut1_spia.pin1 = 1
		dut1_spia.pin2 = 6
		dut1_spia.pin3 = 2
		dut1_spia.pin4 = 5
		dut1_spia.pin5 = 5
		dut1_spia.pin6 = 5
		dut1_spia.pin7 = 5
		dut1_spia.clkEdge=1
		dut1_spia.msbFirst = 1
		
		dut0_spib.addressLen=16
		dut0_spib.packetLen = 24
		dut0_spib.pin0 = 0
		dut0_spib.pin1 = 1
		dut0_spib.pin2 = 5
		dut0_spib.pin3 = 5
		dut0_spib.pin4 = 6
		dut0_spib.pin5 = 2
		dut0_spib.pin6 = 5
		dut0_spib.pin7 = 5
		dut0_spib.clkEdge=1
		dut0_spib.msbFirst = 1
		
		dut1_spib.addressLen=16
		dut1_spib.packetLen = 24
		dut1_spib.pin0 = 0
		dut1_spib.pin1 = 1
		dut1_spib.pin2 = 6
		dut1_spib.pin3 = 2
		dut1_spib.pin4 = 5
		dut1_spib.pin5 = 5
		dut1_spib.pin6 = 5
		dut1_spib.pin7 = 5
		dut1_spib.clkEdge=1
		dut1_spib.msbFirst = 1
		
		lmkregProg.addressLen=16
		lmkregProg.packetLen = 24
		lmkregProg.pin0 = 6
		lmkregProg.pin1 = 2
		lmkregProg.pin2 = 0
		lmkregProg.pin3 = 1
		lmkregProg.pin4 = 5
		lmkregProg.pin5 = 5
		lmkregProg.pin6 = 5
		lmkregProg.pin7 = 5
		lmkregProg.msbFirst = 1
		lmkregProg.clkEdge = 1
		

	
	import j58Wrapper
	reload(j58Wrapper)
	from j58Wrapper import j58WrapperClass
	try:
		myfpga=j58WrapperClass()
	except:
		error("Reset the FPGA and rerun devInit.py")
		raise
	device0=ANUPAM(fileName=Globals.libFolderPath+"//"+"resourceFiles//"+Afe77xxLibraries.folderDirDict[folderName]['dmlName'],regProgDevice=dut0_spib,name='DONOT_OPEN_'+Afe77xxLibraries.folderDirDict[folderName]['dmlName'][:-4]+'_FULL1')
	device1=ANUPAM(fileName=Globals.libFolderPath+"//"+"resourceFiles//"+Afe77xxLibraries.folderDirDict[folderName]['dmlName'],regProgDevice=dut1_spib,name='DONOT_OPEN_'+Afe77xxLibraries.folderDirDict[folderName]['dmlName'][:-4]+'_FULL2')
	cpld=mCPLD_Device.CPLD(fileName=Globals.libFolderPath+"//"+"resourceFiles//EvmCpld.dml",regProgDevice="",name='CPLD')
elif boardType in ('EVM-1Device',"EVM-1DeviceJ58"):
		lmkregProg.addressLen=16
		lmkregProg.packetLen = 24
		lmkregProg.pin0 = 6
		lmkregProg.pin1 = 2
		lmkregProg.pin2 = 0
		lmkregProg.pin3 = 1
		lmkregProg.pin4 = 5
		lmkregProg.pin5 = 5
		lmkregProg.pin6 = 5
		lmkregProg.pin7 = 5
		lmkregProg.msbFirst = 1
		lmkregProg.clkEdge = 1
		if MPSSE==True:
			adcregProg.chipSelect = 0
		else:
			adcregProg.addressLen=16
			adcregProg.packetLen=24
			adcregProg.packetOrder=0
			adcregProg.msbFirst=1
			adcregProg.clkEdge=1
			adcregProg.pin0=0
			adcregProg.pin1=1
			adcregProg.pin2=6
			adcregProg.pin3=2
			adcregProg.pin4=5
			adcregProg.pin5=5
			adcregProg.pin6=5
			adcregProg.pin7=5
			adcregProg.readClkEdge=1
		
		cpldRegProg.addressLen=16
		cpldRegProg.packetLen = 24
		cpldRegProg.pin0 = 5
		cpldRegProg.pin1 = 5
		cpldRegProg.pin2 = 5
		cpldRegProg.pin3 = 5
		cpldRegProg.pin4 = 0
		cpldRegProg.pin5 = 1
		cpldRegProg.pin6 = 6
		cpldRegProg.pin7 = 2
		cpldRegProg.msbFirst = 1
		cpldRegProg.clkEdge = 1
		
		cpld=mCPLD_Device.CPLD(fileName=Globals.libFolderPath+"//"+"resourceFiles//EvmCpld.dml", regProgDevice=cpldRegProg,name='CPLD')
		device=ANUPAM(fileName=Globals.libFolderPath+"//"+"resourceFiles//"+Afe77xxLibraries.folderDirDict[folderName]['dmlName'],regProgDevice=adcregProg,name='DONOT_OPEN_'+Afe77xxLibraries.folderDirDict[folderName]['dmlName'][:-4]+'_FULL')
		if boardType == "EVM-1DeviceJ58":
			import j58Wrapper
			reload(j58Wrapper)
			from j58Wrapper import j58WrapperClass
			try:
				myfpga=j58WrapperClass()
			except:
				error("Reset the FPGA and rerun devInit.py")
				raise
		else:
			myfpga=None
		
else:
	info(boardType)
	if simulationMode==False:
		if MPSSE==False:
			dut0_spia.addressLen=16
			dut0_spia.packetLen = 24
			dut0_spia.pin0 = 0
			dut0_spia.pin1 = 1 
			dut0_spia.pin2 = 6
			dut0_spia.pin3 = 2
			dut0_spia.pin4 = 4
			dut0_spia.pin5 = 4
			dut0_spia.pin6 = 4
			dut0_spia.pin7 = 4
			
			dut1_spia.addressLen=16
			dut1_spia.packetLen = 24
			dut1_spia.pin0 = 0
			dut1_spia.pin1 = 1
			dut1_spia.pin2 = 6
			dut1_spia.pin3 = 4
			dut1_spia.pin4 = 2
			dut1_spia.pin5 = 4
			dut1_spia.pin6 = 4
			dut1_spia.pin7 = 4
			
			dut0_spia.clkEdge=1
			dut1_spia.clkEdge=1
			
			dut0_spia.msbFirst = 1
			dut1_spia.msbFirst = 1
			
			dut0_spib.addressLen=16
			dut0_spib.packetLen = 24
			dut0_spib.pin0 = 0
			dut0_spib.pin1 = 1
			dut0_spib.pin2 = 6
			dut0_spib.pin3 = 4
			dut0_spib.pin4 = 4
			dut0_spib.pin5 = 2
			dut0_spib.pin6 = 4
			dut0_spib.pin7 = 4
			
			dut1_spib.addressLen=16
			dut1_spib.packetLen = 24
			dut1_spib.pin0 = 0
			dut1_spib.pin1 = 1
			dut1_spib.pin2 = 6
			dut1_spib.pin3 = 4
			dut1_spib.pin4 = 4
			dut1_spib.pin5 = 4
			dut1_spib.pin6 = 2
			dut1_spib.pin7 = 4
			
			
			dut0_spib.clkEdge=1
			dut1_spib.clkEdge=1
			
			dut0_spib.msbFirst = 1
			dut1_spib.msbFirst = 1
		else:
			dut0_spia.chipSelect = 0
			dut1_spia.chipSelect = 1
			dut0_spib.chipSelect = 2
			dut1_spib.chipSelect = 3
				
		lmkregProg.addressLen=16
		lmkregProg.packetLen = 24
		lmkregProg.pin0 = 6
		lmkregProg.pin1 = 2
		lmkregProg.pin2 = 0
		lmkregProg.pin3 = 1
		lmkregProg.pin4 = 5
		lmkregProg.pin5 = 5
		lmkregProg.pin6 = 5
		lmkregProg.pin7 = 5
		lmkregProg.msbFirst = 1
		lmkregProg.clkEdge = 1
		
		cpldRegProg.addressLen=16
		cpldRegProg.packetLen = 24
		cpldRegProg.pin0 = 5
		cpldRegProg.pin1 = 5
		cpldRegProg.pin2 = 5
		cpldRegProg.pin3 = 5
		cpldRegProg.pin4 = 0
		cpldRegProg.pin5 = 1
		cpldRegProg.pin6 = 6
		cpldRegProg.pin7 = 2
		cpldRegProg.msbFirst = 1
		cpldRegProg.clkEdge = 1
		
		import j58Wrapper
		reload(j58Wrapper)
		from j58Wrapper import j58WrapperClass
		try:
			myfpga=j58WrapperClass()
		except:
			error("Reset the FPGA and rerun devInit.py")
			raise
	else:
		myfpga=None
	device0=ANUPAM(fileName=Globals.libFolderPath+"//"+"resourceFiles//"+Afe77xxLibraries.folderDirDict[folderName]['dmlName'],regProgDevice=dut0_spib,name='DONOT_OPEN_'+Afe77xxLibraries.folderDirDict[folderName]['dmlName'][:-4]+'_FULL1')
	device1=ANUPAM(fileName=Globals.libFolderPath+"//"+"resourceFiles//"+Afe77xxLibraries.folderDirDict[folderName]['dmlName'],regProgDevice=dut1_spib,name='DONOT_OPEN_'+Afe77xxLibraries.folderDirDict[folderName]['dmlName'][:-4]+'_FULL2')
	cpld=mCPLD_Device.CPLD(fileName=Globals.libFolderPath+"//"+"resourceFiles//EvmCpld.dml",regProgDevice=cpldRegProg,name='CPLD')

lmk=mlmkDevice.LMK(name="LMK Clock Divider",fileName=ASTERIX_DIR+DEVICES_DIR+"LMK04828_form_new.dml",regProgDevice=lmkregProg)
lmk.setResetProperty(lmk.head.page.System.Top_Modes._SW_RESET)

if simulationMode==True:
	cpld=Device(fileName=Globals.libFolderPath+"//"+"resourceFiles//EvmCpld.dml",regProgDevice="",name='CPLD')

#### clk sources

DevClkSource.frequency=368.64e6
DevClkSource.amplitude=0
DevClkSource.frequencySynth=2949.12e6/2
DevClkSource.on=1
DevClkSource.onSynth=1

sigSource00.amplitude=-10
sigSource00.on=1

process=HSCProcessWithILDDCDGC()
engine=HSCEngineWithILDDCDGC(device=myfpga,process=process,clockVariable=clkSource._frequency,inputVariable=sigSource00._frequency)
if boardType!="EVM-1Device":
	myfpga.byte_swap=0
if simulationMode==True:
	if boardType!="EVM-1Device":
		myfpga.delay_time=0
	if boardType in ("BENCH","EVM-1Device","EVM-1DeviceJ58"):
		device.delay_time=0
	else:
		device0.delay_time=0
		device1.delay_time=0
else:
	if boardType!="EVM-1Device":
		if jesdH==True:
			myfpga.delay_time=0.05
		else:
			myfpga.delay_time=0.2
	if boardType in ("BENCH","EVM-1Device","EVM-1DeviceJ58"):
		if MPSSE==False:
			device.delay_time=0.02
		else:
			device.delay_time=0.005
	else:
		if MPSSE==False:
			device0.delay_time=0.02
			device1.delay_time=0.02
		else:
			device0.delay_time=0.004
			device1.delay_time=0.004

if boardType=="HSC1357":
	boardType="HSC1320"

	
import mLogDump
reload(mLogDump)
if boardType in ("BENCH","EVM-1Device","EVM-1DeviceJ58"):
	logDumpInst=mLogDump.logDump(ASTERIX_DIR+DEVICES_DIR+r"\config.txt")
	device.logClassInst=logDumpInst
	if boardType=="BENCH":
		myfpga.logClassInst=logDumpInst
	lmk.logClassInst=logDumpInst
else:
	logDumpInst0=mLogDump.logDump(ASTERIX_DIR+DEVICES_DIR+r"\configDevice0.txt")
	logDumpInst1=mLogDump.logDump(ASTERIX_DIR+DEVICES_DIR+r"\configDevice1.txt")
	device0.logClassInst=logDumpInst0
	device1.logClassInst=logDumpInst1
	myfpga.logClassInst=logDumpInst0
	lmk.logClassInst=logDumpInst0
	
########### Loading the Libraries

import mSetupParams
reload(mSetupParams)
from mSetupParams import setupParams
if boardType=="EVM":
	setupParams.boardType="HSC1320"
else:
	setupParams.boardType=boardType
setupParams.fpgaWriter=writer
setupParams.engine=engine
setupParams.process=process

if simulationMode==True or setupParams.boardType=="EVM-1Device":
	setupParams.skipFpga=True
	setupParams.skipLmk=True
else:
	setupParams.skipFpga=False
	setupParams.skipLmk=False

from mSetupParams import fpgaParamsClass
fpgaParams=fpgaParamsClass()
from mSetupParams import lmkParamsClass
LMKParams=lmkParamsClass()

import mLmk
reload(mLmk)
from mLmk import lmkLib
LMKlibInst=lmkLib(lmk,LMKParams)

if boardType=="BENCH":
	import mFpga
	reload(mFpga)
	from mFpga import fpgaLib
	FPGAlibInst=fpgaLib(myfpga,fpgaParams)
else:
	import mFPGA_J58
	reload(mFPGA_J58)
	from mFPGA_J58 import fpgaLib_J58
	FPGAlibInst=fpgaLib_J58(myfpga,fpgaParams)

if boardType not in ("BENCH","EVM-1Device","EVM-1DeviceJ58","EVM"):
	import CurrentSenseAFE77xx
	reload(CurrentSenseAFE77xx)
	currSensor=CurrentSenseAFE77xx.CurrentSensor(currSenseI2C)
	setupParams.currSensor=currSensor
	
setupParams.fpgaLib=FPGAlibInst
setupParams.lmkLib=LMKlibInst
if boardType not in ("HSC1320","BENCH","HSC1330"):
	setupParams.cpld=cpld

import mFuncDecorator
reload(mFuncDecorator)
from mFuncDecorator import *
def loadLibs(device,dutNo=0):
	import mAfeLibrary
	reload(mAfeLibrary)
	from mAfeLibrary import afeLibrary
	import mAfeParameters
	reload(mAfeParameters)
	from mAfeParameters import systemParams
	from mAfeParameters import systemStatus
	import numpy
	
	device1Refs=deviceRefs()
	sysParams=systemParams()
	sysStatus=systemStatus()
	
	sysParams.chipType=0x10
	device1Refs.device=device
	device1Refs.engine=engine
	device1Refs.process=process
	device1Refs.systemParams=sysParams
	device1Refs.systemStatus=sysStatus
	device1Refs.gpioProg=gpioProg
	device1Refs.lmkParams=LMKParams
	
	sysParams.chipId=chipId
	sysParams.chipVersion=chipVersion
	sysParams.simulationMode=simulationMode
	
	afeInst=afeLibrary(device1Refs,dutNo)
	if len(setupParams.dutInstances)<dutNo:
		setupParams.dutInstances[dutNo]=afeInst
	else:
		setupParams.dutInstances.append(afeInst)
	return (sysParams,sysStatus,afeInst)
	
if boardType in ("BENCH","EVM-1Device","EVM-1DeviceJ58"):
	(sysParams,sysStatus,AFE)=loadLibs(device,0)
else:
	(sysParams0,sysStatus,AFE0)=loadLibs(device0,0)
	(sysParams1,sysStatus,AFE1)=loadLibs(device1,1)
	AFE=AFE1
from common.mMACROConst import MACROConst

####################		
######################
if chipVersion>0x10:
	try:
		if boardType in ("BENCH","EVM-1DeviceJ58","EVM-1Device"):
			imlPath = Globals.libFolderPath+r"\\resourceFiles\\afeiGui\\iGuiTreeBench.iml"
		elif boardType in ("HSC1373"):
			imlPath = Globals.libFolderPath+r"\\resourceFiles\\afeiGui\\iGuiTree.iml"
		
		imlFile=open(imlPath,'r')
		imlFileLines= imlFile.readlines()
		imlFile.close()
		
		libFolderPath = Globals.libFolderPath.split("Afe77xxLibraries")[0]
		
		imlFile=open(imlPath,'w')
		imlFile.close()
		
		imlFile = open(imlPath,'a')
		
		for line in imlFileLines:
			if "Afe77xxLibraries" in line:
				split = line.split("Afe77xxLibraries")
				prefix = split[0].split("path")[0] + 'path="'
				split[0] = libFolderPath
				new = 'Afe77xxLibraries'.join(split)
				new = prefix + new
				imlFile.write(new)
			else:
				imlFile.write(line)
				
		imlFile.close()
		
		
		from iGui import iGui
		import afeiGui
		reload(afeiGui)
		import afeiGui.mAfe77xxSystemParamsiGui
		reload(afeiGui.mAfe77xxSystemParamsiGui)
		from afeiGui.mAfe77xxSystemParamsiGui import afe77xxSystemParamsiGui
		import afeiGui.afe77xxSystemStatusRegs
		reload(afeiGui.afe77xxSystemStatusRegs)
		from afeiGui.afe77xxSystemStatusRegs import afe77xxSystemStatusRegs
		import afeiGui.afe77xxCustomConfig
		reload(afeiGui.afe77xxCustomConfig)
		from afeiGui.afe77xxCustomConfig import afe77xxCustomConfig

		import afeiGui.mAfe77xxPowerMeasurements
		reload(afeiGui.mAfe77xxPowerMeasurements) 
		from afeiGui.mAfe77xxPowerMeasurements import afe77xxCurrentSense
		import afeiGui.mAfe77xxGpioExternalAgc
		reload(afeiGui.mAfe77xxGpioExternalAgc)
		from afeiGui.mAfe77xxGpioExternalAgc import afe77xxGpioExternalAgc
		import afeiGui.mAfe77xxGpioInternalAgc
		reload(afeiGui.mAfe77xxGpioInternalAgc)
		from afeiGui.mAfe77xxGpioInternalAgc import afe77xxGpioInternalAgc
		import afeiGui.afe77xxAdditionalConfig
		reload(afeiGui.afe77xxAdditionalConfig)
		from afeiGui.afe77xxAdditionalConfig import afe77xxAdditionalConfig

		from mAfeConstants import gpioConstants

		import afeiGui.mAfeGuiController
		reload(afeiGui.mAfeGuiController)
		from afeiGui.mAfeGuiController import afeGuiControllerClass

		import afeiGui.afe77xxGpioFinalMapGuiCode
		reload(afeiGui.afe77xxGpioFinalMapGuiCode)
		from afeiGui.afe77xxGpioFinalMapGuiCode import gpioMap

		import afeiGui.genericSelection
		reload(afeiGui.genericSelection)
		from afeiGui.genericSelection import genericSelection

		import afeiGui.gpioTop 
		reload(afeiGui.gpioTop)
		from afeiGui.gpioTop import gpioTop

		import afeiGui.mAfeGuiParams
		reload(afeiGui.mAfeGuiParams)
		from afeiGui.mAfeGuiParams import guiParams


		from PySide import QtGui

		if boardType in ("BENCH","EVM-1DeviceJ58","EVM-1Device","HSC1373"):
			guiCache = guiParams()
			afeiGuiController = afeGuiControllerClass(AFE,gpioConstants) 
			gpioGenericSeliGuiClass = genericSelection(libInstance=AFE,guiControllerInstance=afeiGuiController)
			gpioStatusiGuiClass =gpioMap(libInstance=AFE,guiControllerInstance=afeiGuiController,cpld=cpld)
			afeiGuiController.gpioStatusiGuiClass = gpioStatusiGuiClass
			afeiGuiController.gpioGenericSeliGuiClass = gpioGenericSeliGuiClass
			afeiGuiController.gpioStatusiGuiClass = gpioStatusiGuiClass
			gpioGroupSelection = gpioTop(libInstance=AFE,guiControllerInstance=afeiGuiController)
			
			systemParamClassiGui = afe77xxSystemParamsiGui(libInstance=AFE, cache=guiCache, gpio=cpld,guiControllerInstance=afeiGuiController,lmkParams=LMKParams,FPGA=myfpga)
			afeiGuiController.sysParamClassInst = systemParamClassiGui
			customConfig=afe77xxCustomConfig(libInstance=AFE, cache=guiCache,guiControllerInstance=afeiGuiController)
			additionalConfig = afe77xxAdditionalConfig(libInstance=AFE, cache = guiCache,guiControllerInstance=afeiGuiController)
			statusRegisters=afe77xxSystemStatusRegs(libInstance=AFE,guiControllerInstance=afeiGuiController)
			afe77xxiGui= iGui(fileName = Globals.libFolderPath+"//"+"resourceFiles//"+r"/afeiGui/iGuiTreeBench.iml")
			guiCache.guiInst = afe77xxiGui
			afeiGuiController.guiInstance = afe77xxiGui
			
			for i in [1,2,3,4,5,6]:
				eval("afe77xxiGui.mainWindow.changeTab("+str(i)+")")
				eval("afe77xxiGui.mainWindow.stackWidget.currentWidget().svgWidget.resize(1600,950)")
			# 	eval("afe77xxiGui.mainWindow.resize(1642,992)")
				afe77xxiGui.mainWindow.stackWidget.currentWidget().scrollArea.setWidgetResizable(False)
			Globals.mainWindowOpen=True
			def closeMainWindow():
				if Globals.mainWindowOpen:
					mainWindow.hide()
					Globals.mainWindowOpen = False
				else:
					mainWindow.show()
					Globals.mainWindowOpen = True
			a = QtGui.QAction(afe77xxiGui.mainWindow)
			a.setShortcut("ctrl+L")
			a.triggered.connect(closeMainWindow)
			afe77xxiGui.mainWindow.listWidget.hide()
			afe77xxiGui.mainWindow.resize(1642,992)
			afe77xxiGui.mainWindow.setMaximumWidth(1643)
			afe77xxiGui.mainWindow.setMaximumHeight(992)
			afe77xxiGui.mainWindow.changeTab(2)
			afe77xxiGui.mainWindow.setWindowTitle("AFE77xx iGui")
			afe77xxiGui.mainWindow.addAction(mainWindow.actionClearLog)
			afe77xxiGui.mainWindow.addAction(a)
			afe77xxiGui.show()
			
		elif boardType in ("HSC1373",):
			guiCache0 = guiParams()
			guiCache1 = guiParams()
			
			afeiGuiController = afeGuiControllerClass(AFE0,gpioConstants) 
			gpioGenericSeliGuiClass = genericSelection(libInstance=AFE0,guiControllerInstance=afeiGuiController)
			gpioStatusiGuiClass =gpioMap(libInstance=AFE0,guiControllerInstance=afeiGuiController)
			afeiGuiController.gpioStatusiGuiClass = gpioStatusiGuiClass
			afeiGuiController.gpioGenericSeliGuiClass = gpioGenericSeliGuiClass
			
			systemParamClassiGui0 = afe77xxSystemParamsiGui(libInstance=AFE0, cache=guiCache0, gpio=cpld)
			systemParamClassiGui1 = afe77xxSystemParamsiGui(libInstance=AFE1, cache=guiCache1, gpio=cpld)
			additionalConfig0 = afe77xxAdditionalConfig(libInstance=AFE0, cache = guiCache0)
			additionalConfig1 = afe77xxAdditionalConfig(libInstance=AFE1, cache = guiCache1)
			customConfig0=afe77xxCustomConfig(libInstance=AFE0, cache=guiCache0)
			customConfig1=afe77xxCustomConfig(libInstance=AFE1, cache=guiCache1)
			statusRegisters0=afe77xxSystemStatusRegs(libInstance=AFE0)
			statusRegisters1=afe77xxSystemStatusRegs(libInstance=AFE1)
			powerMeasurements = afe77xxCurrentSense(cache=guiCache0)
			gpioInternal = afe77xxGpioInternalAgc(libInstance=AFE0,gpio=cpld)
			gpioExternal = afe77xxGpioExternalAgc(libInstance=AFE0,gpio=cpld)
			gpioStatusiGuiClass =gpioMap(fileName = r"PATH_TO_SVG_FILE",libInstance=AFE0,guiControllerInstance=afeiGuiController)
			gpioGroupSelection = gpioTop(libInstance=AFE0,guiControllerInstance=afeiGuiController)
			afe77xxiGui= iGui(fileName = Globals.libFolderPath+"//resourceFiles//"+r"\\afeiGui\iGuiTree.iml")
			afeiGuiController.guiInstance = afe77xxiGui
	

	
	except:
		error("Couldn't load iGui")
###########


if boardType in ("BENCH",):
	mainWindow.restoreSession(PROJECTS_DIR+r"\AFE77xx\bringup\customGui.astx")
elif boardType in ("EVM-1DeviceJ58","EVM-1Device"):
	mainWindow.restoreSession(PROJECTS_DIR+r"\AFE77xx\bringup\customGui1XEvm.astx")
else:
	mainWindow.restoreSession(PROJECTS_DIR+r"\AFE77xx\bringup\customGuiEvm.astx")

Connect(process.fftImdParams._fin1,sigSource00._frequency,1,1)
engine.sampleNo=32768
process.complexfftParam.ignoreImdBinsForSnr=1
process.complexfftParam.finSkipBins=200

process.complexfftParam.ignoreBinsAroundFin1AndFin2ForSnr=1
process.complexfftParam.ignoreImdBinsForSnr=1
process.complexfftParam.finSkipBins=200
process.complexfftParam.ignoreFinImage=1
process.complexfftPlot.harmonicsNo=1

info(gc.collect())
device.rawWriteLogsFile=ASTERIX_DIR+DEVICES_DIR+r"\test.txt"#"D:\AFE77xx_config/testBroadcast.txt"
#myfpga.rawWriteLogsFile=device.rawWriteLogsFile
lmk.rawWriteLogsFile=device.rawWriteLogsFile

import gc
gc.collect()
from mDummySignalSource import DummySignalSource
from HSCProgrammer import QPort
from KintexProgrammer import KintexSPIProgrammer
from JESDCapture import JESDCapture
import d2xx
from USBCaptureTrig import USBCaptureTrig
from USBHSCProgrammer import USBQPort

try:
	from USBHSCProgrammer import i2cPort
except:
	pass
from basicPlots import BasicPlot
import numpy as np
import time
from logPlots import Log
import globalDefs as Globals
from mKeysightVectorSignalGenerator import KeysightE8267D
from mKeithleyPowerSupply import Keithley2230G	
import fpgawrite
import sys,os

import mpsseSPI
reload(mpsseSPI)

boardType="EVM-1DeviceJ58"#"HSC1373"##"EVM"#"EVM-1DeviceJ58"#	#"HSC1320"#"EVM-1Device"#"HSC1330"#
jesdH=False#True#
chipId=0x77
chipVersion=0x11
import Afe77xxLibraries
reload(Afe77xxLibraries)
folderName=Afe77xxLibraries.getFolderName(chipId,chipVersion)
info(folderName)


#### signal and clock source
sigSource00=DummySignalSource(addr="Null",name="Signal Source")

DevClkSource=DummySignalSource(addr="Null",name="Device Source clk")
clkSource=DummySignalSource(addr="Null",name="RF Source clk")


MPSSE=True#True#

# FPGA reset and reload
def fpgaHandleInstance():
	if("fpgaResetHandle" not in globals()):
		for i in range(d2xx.createDeviceInfoList()):
			identifier=d2xx.getDeviceInfoDetail(i)['description']
			if(identifier=="TSW14J58_CTRL B"):
				qportAddr="TSW14J58_CTRL B"
				fpgaResetFtdi=USBQPort(name="FPGA reset",addr=qportAddr)
				fpgaResetFtdi.pin0=4  #fpga resetZ=1
				fpgaResetFtdi.pin1=5
				fpgaResetFtdi.pin2=4  #program sel=1
				fpgaResetFtdi.pin3=5
				fpgaResetFtdi.pin4=4  #fpga progZ=1
				fpgaResetFtdi.pin5=5
				fpgaResetFtdi.pin6=5
				fpgaResetFtdi.pin7=5
				Globals.fpgaResetFtdi = fpgaResetFtdi
				fpgaResetCheck = 0
				return fpgaResetFtdi
			else:
				fpgaResetCheck = 1
		if fpgaResetCheck:#(i==d2xx.createDeviceInfoList()-1):
			warning("Automatic reset of fpga will not be supported.")
try:
	if boardType=="EVM-1DeviceJ58":
		fpgaHandleInstance()
	else:
		warning("Automatic reset of fpga will not be supported.")
except:
	warning("Automatic reset of fpga will not be supported.")
	pass
	
def reloadFpga():
	if("fpgaResetFtdi" in globals()):
		log("Programing FPGA ....")
		Globals.fpgaResetFtdi.pin4=3
		delay(0.3)
		Globals.fpgaResetFtdi.pin4=4
		delay(0.2)
		log("Programing FPGA Done")
	else:
		error("FPGA Reset device not found")
def resetFpga(ver=0):
	if("fpgaResetFtdi" in globals()):
		log("Resetting FPGA ....")
		for i in range(2):
			if(ver==1):
				fpgaResetFtdi.pin0=3
				delay(0.5)
				fpgaResetFtdi.pin0=4
				delay(0.8)
			else:
				fpgaResetFtdi.pin0=4
				delay(0.5)
				fpgaResetFtdi.pin0=3
				delay(0.8)
		log("Resetting FPGA Done")
		if("myfpga" in globals()):
			myfpga.Reconnect()
	else:
		error("FPGA Reset device not found")

for qportId in ('A','B','C','D'):
	exec("qportName"+qportId+"=np.array([])")
	for i in range(d2xx.createDeviceInfoList()):
		try:
			identifier=d2xx.getDeviceInfoDetail(i)['description'][-1]
		except:
			identifier=""
		if(identifier==qportId):
			exec("qportName"+qportId+"=np.append(qportName"+qportId+",d2xx.getDeviceInfoDetail(i)['description'][:-2])")
for qportName in qportNameA:
	if(qportName in ['Anupam Main USB','Quad RS232-HS']):
		if((qportName in qportNameB) and (qportName in qportNameC) and (qportName in qportNameD)):
			break


try:
	if boardType=="BENCH":
		jtagregProg = USBQPort(name="Kintex RegProgrammer",addr="Anupam Main USB C")
		adcregProg = USBQPort(name="Kintex RegProgrammer",addr="Anupam Main USB D")
		lmkregProg = USBQPort(name="Kintex RegProgrammer",addr="Anupam Main USB B")
		fpgaregProg = USBQPort(name="Kintex RegProgrammer",addr="Anupam Main USB B")
		# capture_port = USBQPort(name="Kintex RegProgrammer",addr="Quad RS232-HS A")
		capDev = USBCaptureTrig(name="Kintex Capture Card");#,addrB="Quad RS232-HS B",addrC="Quad RS232-HS C")
		writer=fpgawrite.fpgaWriter()
		gpioProg= USBQPort(name="Kintex RegProgrammer",addr="Anupam Main USB C") 
	elif boardType=="HSC1330":
		jtagregProg = USBQPort(name="Kintex RegProgrammer",addr="Anupam Main USB C")
		adcregProg = USBQPort(name="Kintex RegProgrammer",addr="Anupam Main USB B")
		lmkregProg = USBQPort(name="Kintex RegProgrammer",addr="Anupam Main USB D")
		fpgaregProg = USBQPort(name="Kintex RegProgrammer",addr="Anupam Main USB D")
		# capture_port = USBQPort(name="Kintex RegProgrammer",addr="Quad RS232-HS A")
		capDev = USBCaptureTrig(name="Kintex Capture Card");#,addrB="Quad RS232-HS B",addrC="Quad RS232-HS C")
		writer=fpgawrite.fpgaWriter()
		gpioProg= USBQPort(name="Kintex RegProgrammer",addr="Anupam Main USB C") 
	elif boardType in ("EVM-1DeviceJ58","EVM-1Device"):
		if MPSSE==True:
			adcregProg = mpsseSPI.spi(addr=qportName+" A")#"Anupam Main USB A"
			adcregProg.clockDivider=4
		else:
			adcregProg = USBQPort(name="Kintex RegProgrammer",addr=qportName+" A")#"Anupam Main USB A"
		lmkregProg = USBQPort(name="LMK RegProgrammer",addr=qportName+" D")#"Anupam Main USB D"
		capDev=""
		fpgaregProg=""
		writer=""
		cpldRegProg=USBQPort(name="CPLD RegProgrammer",addr=qportName+" C")#"Anupam Main USB D"
		gpioProg=""
# 		regProgBusC=USBQPort(name="regProgBus RegProgrammer",addr=qportName+" C")#"Anupam Main USB C"
	else:
		if boardType=="HSC1320":
			dut0_spia= USBQPort(name="Kintex RegProgrammer",addr="Quad RS232-HS B")
			dut1_spia= USBQPort(name="Kintex RegProgrammer",addr="Quad RS232-HS B") 
			dut0_spib= USBQPort(name="Kintex RegProgrammer",addr="Quad RS232-HS C")
			dut1_spib= USBQPort(name="Kintex RegProgrammer",addr="Quad RS232-HS C")
		else:
			if MPSSE==True:
				dut0_spia= mpsseSPI.spi(addr="Quad RS232-HS A")
				dut1_spia= mpsseSPI.spi(addr="Quad RS232-HS A") 
				dut0_spib= mpsseSPI.spi(addr="Quad RS232-HS A")
				dut1_spib= mpsseSPI.spi(addr="Quad RS232-HS A")
				dut0_spia.clockDivider=4
				dut0_spib.clockDivider=4
				dut1_spia.clockDivider=4
				dut1_spib.clockDivider=4
			else:
				dut0_spia= USBQPort(name="Kintex RegProgrammer",addr="Quad RS232-HS A")
				dut1_spia= USBQPort(name="Kintex RegProgrammer",addr="Quad RS232-HS A") 
				dut0_spib= USBQPort(name="Kintex RegProgrammer",addr="Quad RS232-HS A")
				dut1_spib= USBQPort(name="Kintex RegProgrammer",addr="Quad RS232-HS A")
			
		try:
			currSenseI2C = i2cPort(name="i2c Programmer",addr="Quad RS232-HS B", CLK_pin = 0, SDAI_pin = 2, SDAO_pin = 1)
			currSenseI2C.pin0 = 0
			currSenseI2C.pin1 = 1
			currSenseI2C.pin2 = 5
		except:
			currSenseI2C=""
		cpldRegProg=USBQPort(name="Kintex RegProgrammer",addr="Quad RS232-HS D")
		
		info("Device handles instantiated")
		writer="Dummy"
		sys.path.append(ASTERIX_DIR+r"\lib\projectsRootDir")
		lmkregProg = USBQPort(name="Kintex RegProgrammer",addr="Quad RS232-HS D")
		gpioProg=""
	simulationMode=False
except:
	error("Got an error Connecting to hardware. Running in Simulation Mode.")
	boardType="BENCH"
	writer="Dummy"
	if boardType=="BENCH":
		adcregProg = ""
		fpgaregProg = ""
		capDev=""
	else:
		dut0_spia= ""
		dut1_spia= ""
		dut0_spib= ""
		dut1_spib= ""
	lmkregProg = ""
	simulationMode=True
	gpioProg=""
	cpldRegProg=""
	
class HWReset(object):
	"""docstring for HWReset"""
	def __init__(self, regProgDevice=None, pin_no=None):
		super(HWReset, self).__init__()
		self.regProgDevice = regProgDevice
		self.pin_no = pin_no
		if self.regProgDevice!=None:
			for pin in range(8):
				exec("self.regProgDevice.pin" + str(pin) + "=5")
		else:
			pass

	def toggle(self):
		if self.regProgDevice!=None:
			exec("self.regProgDevice.pin" + str(self.pin_no) + "=3")
			delay(0.1)
			exec("self.regProgDevice.pin" + str(self.pin_no) + "=4")
		else:
			pass

if boardType == "HSC1373":
	hwResetQPort= USBQPort(name="Kintex RegProgrammer",addr="Quad RS232-HS C")		
	hwResetHandle = HWReset(regProgDevice = hwResetQPort, pin_no=0)
else:
	hwResetHandle = HWReset()
Globals.simulationMode = simulationMode

#======
#Executing .. AFE77xx/J58_initial/setup_J58.py
#Start Time 2024-02-15 15:34:33.477000 
AFE77xxLibraryPG1P1
Automatic reset of fpga will not be supported.
spi - USB Instrument created.
resetDevice
Purge
MPSSE mode set
LMK RegProgrammer - USB Instrument created.
CPLD RegProgrammer - USB Instrument created.
#Done executing .. AFE77xx/J58_initial/setup_J58.py
#End Time 2024-02-15 15:34:39.374000
#Execution Time = 5.89700007439 s 
#================ ERRORS:0, WARNINGS:1 ================#
#======
#Executing .. AFE77xx/J58_initial/devInit_J58.py
#Start Time 2024-02-15 15:34:41.050000 
Version : 0x104204b
Connected to Capture Card
Successfully Loaded the Libraries.
Could not find attribute _logWidget in systemParamClassiGui
Couldn't load iGui
13
#Done executing .. AFE77xx/J58_initial/devInit_J58.py
#End Time 2024-02-15 15:35:23.750000
#Execution Time = 42.7000000477 s 
#================ ERRORS:1, WARNINGS:1 ================#
#======
#Executing .. AFE77xx/J58_initial/Alpha_EVM_bringup.py
#Start Time 2024-02-15 15:35:32.142000 
DONOT_OPEN_Afe77xxPG1p1_FULL - Device registers reset.
chipType: 0xff
chipId: 0xffff
chipVersion: 0xff
2T2R1F Number: 0
Valid Configuration: True
laneRateRx: 4915.2
laneRateFb: 4915.2
laneRateTx: 4915.2
2T2R1F Number: 1
Valid Configuration: True
laneRateRx: 4915.2
laneRateFb: 4915.2
laneRateTx: 4915.2
SPI not working.
#Done executing .. AFE77xx/J58_initial/Alpha_EVM_bringup.py
#End Time 2024-02-15 15:35:34.307000
#Execution Time = 2.16499996185 s 
#================ ERRORS:1, WARNINGS:0 ================#
#======
#Executing .. AFE77xx/J58_initial/Alpha_EVM_bringup.py
#Start Time 2024-02-15 15:35:41.834000 
DONOT_OPEN_Afe77xxPG1p1_FULL - Device registers reset.
chipType: 0xa
chipId: 0x77
chipVersion: 0x11
2T2R1F Number: 0
Valid Configuration: True
laneRateRx: 4915.2
laneRateFb: 4915.2
laneRateTx: 4915.2
2T2R1F Number: 1
Valid Configuration: True
laneRateRx: 4915.2
laneRateFb: 4915.2
laneRateTx: 4915.2
Resetting FPGA.
Reset the FPGA and try again.
LMK Clock Divider - Device registers reset.
lmk.writeReg(000,0x00000080)
lmk.writeReg(000,0x00000000)
LMK Clock Divider - Device registers reset.
lmk.writeReg(000,0x00000080)
lmk.writeReg(000,0x00000000)
lmk.writeReg(000,0x00000080)
lmk.writeReg(000,0x00000000)
lmk.writeReg(330,0x00000003)
lmk.writeReg(330,0x00000033)
lmk.writeReg(000,0x00000000)
lmk.writeReg(002,0x00000000)
lmk.writeReg(256,0x0000000C)
lmk.writeReg(256,0x0000000C)
lmk.writeReg(256,0x0000000C)
lmk.writeReg(257,0x00000055)
lmk.writeReg(257,0x00000055)
lmk.writeReg(259,0x00000001)
lmk.writeReg(259,0x00000001)
lmk.writeReg(259,0x00000001)
lmk.writeReg(260,0x00000000)
lmk.writeReg(260,0x00000000)
lmk.writeReg(260,0x00000020)
lmk.writeReg(260,0x00000020)
lmk.writeReg(261,0x00000000)
lmk.writeReg(261,0x00000000)
lmk.writeReg(262,0x00000018)
lmk.writeReg(262,0x00000018)
lmk.writeReg(262,0x00000010)
lmk.writeReg(262,0x00000010)
lmk.writeReg(262,0x00000090)
lmk.writeReg(263,0x00000001)
lmk.writeReg(263,0x00000001)
lmk.writeReg(263,0x00000011)
lmk.writeReg(263,0x00000011)
lmk.writeReg(264,0x00000006)
lmk.writeReg(264,0x00000026)
lmk.writeReg(264,0x00000066)
lmk.writeReg(265,0x00000055)
lmk.writeReg(265,0x00000055)
lmk.writeReg(267,0x00000001)
lmk.writeReg(267,0x00000001)
lmk.writeReg(267,0x00000001)
lmk.writeReg(268,0x00000000)
lmk.writeReg(268,0x00000000)
lmk.writeReg(268,0x00000020)
lmk.writeReg(268,0x00000020)
lmk.writeReg(269,0x00000000)
lmk.writeReg(269,0x00000000)
lmk.writeReg(270,0x00000018)
lmk.writeReg(270,0x00000018)
lmk.writeReg(270,0x00000010)
lmk.writeReg(270,0x00000010)
lmk.writeReg(270,0x00000090)
lmk.writeReg(271,0x00000004)
REFCLOCK is used from LMK source, ensure board connections are ok to do the same
lmk.writeReg(271,0x00000004)
lmk.writeReg(271,0x00000014)
lmk.writeReg(271,0x00000014)
lmk.writeReg(272,0x00000008)
lmk.writeReg(272,0x00000008)
lmk.writeReg(272,0x00000008)
lmk.writeReg(273,0x00000055)
lmk.writeReg(273,0x00000055)
lmk.writeReg(275,0x00000000)
lmk.writeReg(275,0x00000000)
lmk.writeReg(275,0x00000000)
lmk.writeReg(276,0x00000000)
lmk.writeReg(276,0x00000000)
lmk.writeReg(276,0x00000000)
lmk.writeReg(276,0x00000000)
lmk.writeReg(277,0x00000000)
lmk.writeReg(277,0x00000000)
lmk.writeReg(278,0x00000011)
lmk.writeReg(278,0x00000011)
lmk.writeReg(278,0x00000019)
lmk.writeReg(278,0x00000019)
lmk.writeReg(278,0x00000099)
lmk.writeReg(279,0x00000000)
lmk.writeReg(279,0x00000000)
lmk.writeReg(279,0x00000000)
lmk.writeReg(279,0x00000000)
lmk.writeReg(280,0x00000018)
lmk.writeReg(280,0x00000018)
lmk.writeReg(280,0x00000018)
lmk.writeReg(281,0x00000055)
lmk.writeReg(281,0x00000055)
lmk.writeReg(283,0x00000000)
lmk.writeReg(283,0x00000000)
lmk.writeReg(283,0x00000000)
lmk.writeReg(284,0x00000000)
lmk.writeReg(284,0x00000000)
lmk.writeReg(284,0x00000020)
lmk.writeReg(284,0x00000020)
lmk.writeReg(285,0x00000000)
lmk.writeReg(285,0x00000000)
lmk.writeReg(286,0x00000011)
lmk.writeReg(286,0x00000011)
lmk.writeReg(286,0x00000019)
lmk.writeReg(286,0x00000019)
lmk.writeReg(286,0x00000099)
lmk.writeReg(287,0x00000000)
lmk.writeReg(287,0x00000000)
lmk.writeReg(287,0x00000000)
lmk.writeReg(287,0x00000000)
lmk.writeReg(288,0x0000000C)
lmk.writeReg(288,0x0000000C)
lmk.writeReg(288,0x0000000C)
lmk.writeReg(289,0x00000055)
lmk.writeReg(289,0x00000055)
lmk.writeReg(291,0x00000000)
lmk.writeReg(291,0x00000000)
lmk.writeReg(291,0x00000000)
lmk.writeReg(292,0x00000000)
lmk.writeReg(292,0x00000000)
lmk.writeReg(292,0x00000000)
lmk.writeReg(292,0x00000000)
lmk.writeReg(293,0x00000000)
lmk.writeReg(293,0x00000000)
lmk.writeReg(294,0x00000011)
lmk.writeReg(294,0x00000011)
lmk.writeReg(294,0x00000019)
lmk.writeReg(294,0x00000019)
lmk.writeReg(294,0x00000099)
lmk.writeReg(295,0x00000001)
lmk.writeReg(295,0x00000001)
lmk.writeReg(295,0x00000011)
lmk.writeReg(295,0x00000011)
lmk.writeReg(296,0x00000008)
lmk.writeReg(296,0x00000008)
lmk.writeReg(296,0x00000008)
lmk.writeReg(297,0x00000055)
lmk.writeReg(297,0x00000055)
lmk.writeReg(299,0x00000000)
lmk.writeReg(299,0x00000000)
lmk.writeReg(299,0x00000000)
lmk.writeReg(300,0x00000000)
lmk.writeReg(300,0x00000000)
lmk.writeReg(300,0x00000000)
lmk.writeReg(300,0x00000000)
lmk.writeReg(301,0x00000000)
lmk.writeReg(301,0x00000000)
lmk.writeReg(302,0x00000011)
lmk.writeReg(302,0x00000011)
lmk.writeReg(302,0x00000019)
lmk.writeReg(302,0x00000019)
lmk.writeReg(302,0x00000099)
lmk.writeReg(303,0x00000000)
lmk.writeReg(303,0x00000000)
lmk.writeReg(303,0x00000000)
lmk.writeReg(303,0x00000000)
lmk.writeReg(304,0x0000000C)
lmk.writeReg(304,0x0000000C)
lmk.writeReg(304,0x0000000C)
lmk.writeReg(305,0x00000055)
lmk.writeReg(305,0x00000055)
lmk.writeReg(307,0x00000000)
lmk.writeReg(307,0x00000000)
lmk.writeReg(307,0x00000000)
lmk.writeReg(308,0x00000000)
lmk.writeReg(308,0x00000000)
lmk.writeReg(308,0x00000020)
lmk.writeReg(308,0x00000020)
lmk.writeReg(309,0x00000000)
lmk.writeReg(309,0x00000000)
lmk.writeReg(310,0x00000019)
lmk.writeReg(310,0x00000019)
lmk.writeReg(310,0x00000011)
lmk.writeReg(310,0x00000011)
lmk.writeReg(310,0x00000091)
lmk.writeReg(311,0x00000001)
lmk.writeReg(311,0x00000001)
lmk.writeReg(311,0x00000001)
lmk.writeReg(311,0x00000001)
lmk.writeReg(312,0x00000000)
lmk.writeReg(312,0x00000000)
lmk.writeReg(312,0x00000020)
lmk.writeReg(313,0x00000003)
lmk.writeReg(313,0x00000003)
lmk.writeReg(315,0x00000000)
lmk.writeReg(314,0x00000003)
lmk.writeReg(317,0x00000008)
lmk.writeReg(316,0x00000000)
lmk.writeReg(318,0x00000003)
lmk.writeReg(319,0x00000000)
lmk.writeReg(319,0x00000000)
lmk.writeReg(319,0x00000000)
lmk.writeReg(319,0x00000000)
lmk.writeReg(320,0x00000006)
lmk.writeReg(320,0x00000004)
lmk.writeReg(320,0x00000000)
lmk.writeReg(320,0x00000000)
lmk.writeReg(320,0x00000000)
lmk.writeReg(320,0x00000000)
lmk.writeReg(320,0x00000000)
lmk.writeReg(320,0x00000000)
lmk.writeReg(321,0x00000000)
lmk.writeReg(321,0x00000000)
lmk.writeReg(321,0x00000000)
lmk.writeReg(321,0x00000000)
lmk.writeReg(321,0x00000000)
lmk.writeReg(321,0x00000000)
lmk.writeReg(321,0x00000000)
lmk.writeReg(321,0x00000000)
lmk.writeReg(322,0x00000000)
lmk.writeReg(323,0x00000092)
lmk.writeReg(323,0x00000092)
lmk.writeReg(323,0x00000092)
lmk.writeReg(323,0x00000092)
lmk.writeReg(323,0x00000092)
lmk.writeReg(323,0x00000092)
lmk.writeReg(323,0x00000012)
lmk.writeReg(324,0x00000001)
lmk.writeReg(324,0x00000003)
lmk.writeReg(324,0x00000007)
lmk.writeReg(324,0x0000000F)
lmk.writeReg(324,0x0000001F)
lmk.writeReg(324,0x0000003F)
lmk.writeReg(324,0x0000007F)
lmk.writeReg(324,0x000000FF)
lmk.writeReg(326,0x00000018)
lmk.writeReg(326,0x00000018)
lmk.writeReg(326,0x00000018)
lmk.writeReg(326,0x00000010)
lmk.writeReg(326,0x00000010)
lmk.writeReg(326,0x00000010)
lmk.writeReg(327,0x0000003A)
lmk.writeReg(327,0x0000003A)
lmk.writeReg(327,0x0000001A)
lmk.writeReg(327,0x0000001A)
lmk.writeReg(328,0x00000002)
lmk.writeReg(328,0x00000002)
lmk.writeReg(329,0x00000042)
lmk.writeReg(329,0x00000042)
lmk.writeReg(329,0x00000042)
lmk.writeReg(332,0x00000000)
lmk.writeReg(331,0x00000016)
lmk.writeReg(331,0x00000016)
lmk.writeReg(331,0x00000016)
lmk.writeReg(331,0x00000016)
lmk.writeReg(331,0x00000016)
lmk.writeReg(331,0x00000016)
lmk.writeReg(333,0x00000000)
lmk.writeReg(334,0x00000000)
lmk.writeReg(334,0x000000C0)
lmk.writeReg(335,0x0000007F)
lmk.writeReg(336,0x00000003)
lmk.writeReg(336,0x00000003)
lmk.writeReg(336,0x00000003)
lmk.writeReg(336,0x00000003)
lmk.writeReg(336,0x00000003)
lmk.writeReg(336,0x00000043)
lmk.writeReg(338,0x00000000)
lmk.writeReg(337,0x00000002)
lmk.writeReg(340,0x00000078)
lmk.writeReg(339,0x00000000)
lmk.writeReg(342,0x0000007D)
lmk.writeReg(341,0x00000000)
lmk.writeReg(344,0x00000096)
lmk.writeReg(343,0x00000000)
lmk.writeReg(346,0x00000000)
lmk.writeReg(345,0x00000006)
lmk.writeReg(347,0x000000D4)
lmk.writeReg(347,0x000000D4)
lmk.writeReg(347,0x000000D4)
lmk.writeReg(347,0x000000D4)
lmk.writeReg(349,0x00000000)
lmk.writeReg(348,0x00000020)
lmk.writeReg(350,0x00000000)
lmk.writeReg(350,0x00000000)
lmk.writeReg(351,0x0000000B)
lmk.writeReg(351,0x0000000B)
lmk.writeReg(353,0x00000001)
lmk.writeReg(352,0x00000000)
lmk.writeReg(354,0x0000005C)
lmk.writeReg(354,0x0000005C)
lmk.writeReg(354,0x00000044)
lmk.writeReg(354,0x00000044)
lmk.writeReg(357,0x0000000C)
lmk.writeReg(356,0x00000000)
lmk.writeReg(355,0x00000000)
lmk.writeReg(358,0x00000000)
lmk.writeReg(360,0x0000000C)
lmk.writeReg(359,0x00000000)
lmk.writeReg(358,0x00000000)
lmk.writeReg(361,0x00000058)
lmk.writeReg(361,0x00000058)
lmk.writeReg(361,0x00000058)
lmk.writeReg(361,0x00000058)
lmk.writeReg(363,0x00000000)
lmk.writeReg(362,0x00000020)
lmk.writeReg(364,0x00000000)
lmk.writeReg(364,0x00000000)
lmk.writeReg(365,0x00000000)
lmk.writeReg(365,0x00000000)
lmk.writeReg(366,0x00000013)
lmk.writeReg(366,0x00000013)
lmk.writeReg(380,0x00000015)
lmk.writeReg(381,0x0000000F)
Reset the FPGA and try again.
Fuse farm load autoload done successful
No autload error
Purge
Purge
MACRO_READY: True
MACRO_ACK: True
MACRO_DONE: True
MACRO_ERROR: False
Purge
MACRO_READY: True
MACRO_ACK: True
MACRO_DONE: True
MACRO_ERROR: False
MACRO_READY: True
MACRO_ACK: True
MACRO_DONE: True
MACRO_ERROR: False
SPIA has got control of PLL pages
pll0: True; LO Frequency: 4849.86
pll1: True; LO Frequency: 2949.12
PLL Pages SPI control relinquished.
FB DSA 4.9G Band
Purge
Purge
Purge
*TX IQMC Patch Apply*
SPIA has got control of PLL pages
PLL Pages SPI control relinquished.
FW_VERSION=0x11119e
attack_value: 2899.74593284
decay_value: 1829.61599345
attack_value: 3253.56844943
decay_value: 2052.86290894
attack_value: 2899.74593284
decay_value: 1829.61599345
attack_value: 3253.56844943
decay_value: 2052.86290894
SPIA has got control of PLL pages
PLL Pages SPI control relinquished.
Sysref to RX AB, Read: 3; expected: 3
Sysref to RX CD, Read: 3; expected: 3
Sysref to FB A, Read: 1; expected: 1
Sysref to FB D, Read: 1; expected: 1
Sysref to TX AB, Read: 255; expected: 7
Sysref to TX CD, Read: 255; expected: 7
Digital Clock, Read: True; expected: 1
Sysref to Digital, Read: True; expected: 1
Sysref to Analog, Read: 65535; expected: 7
lmk.writeReg(262,0x000000F0)
###########Device DAC JESD-RX 0 Link Status###########
LOS Indicator for (Serdes Loss of signal) lane 0: 1
Frame Sync error (unexpected k28.5) for lane 0: 1
LOS Indicator for (Serdes Loss of signal) lane 1: 1
Frame Sync error (unexpected k28.5) for lane 1: 1
LOS Indicator for (Serdes Loss of signal) lane 2: 1
Frame Sync error (unexpected k28.5) for lane 2: 1
LOS Indicator for (Serdes Loss of signal) lane 3: 1
Frame Sync error (unexpected k28.5) for lane 3: 1
lane0 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane1 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane2 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane3 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane0 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
lane1 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
lane2 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
lane3 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
CS State TX0: 0b11111111 . It is expected to be 0b00001010
FS State TX0: 0b11111111 . It is expected to be 0b00000101
Couldn't get the link up for device RX: 0; Alarms: 0xfffffffffffffff7L
###################################
lmk.writeReg(262,0x000000F1)
lmk.writeReg(262,0x000000F0)
###########Device DAC JESD-RX 1 Link Status###########
LOS Indicator for (Serdes Loss of signal) lane 0: 1
Frame Sync error (unexpected k28.5) for lane 0: 1
LOS Indicator for (Serdes Loss of signal) lane 1: 1
Frame Sync error (unexpected k28.5) for lane 1: 1
LOS Indicator for (Serdes Loss of signal) lane 2: 1
Frame Sync error (unexpected k28.5) for lane 2: 1
LOS Indicator for (Serdes Loss of signal) lane 3: 1
Frame Sync error (unexpected k28.5) for lane 3: 1
lane0 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane1 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane2 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane3 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane0 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
lane1 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
lane2 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
lane3 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
CS State TX0: 0b11111111 . It is expected to be 0b00001010
FS State TX0: 0b11111111 . It is expected to be 0b00000101
Couldn't get the link up for device RX: 1; Alarms: 0xfffffffffffffff7L
###################################
lmk.writeReg(262,0x000000F1)
lmk.writeReg(262,0x000000F0)
lmk.writeReg(262,0x000000F1)
###########Device DAC JESD-RX 0 Link Status###########
LOS Indicator for (Serdes Loss of signal) lane 0: 1
Frame Sync error (unexpected k28.5) for lane 0: 1
LOS Indicator for (Serdes Loss of signal) lane 1: 1
Frame Sync error (unexpected k28.5) for lane 1: 1
LOS Indicator for (Serdes Loss of signal) lane 2: 1
Frame Sync error (unexpected k28.5) for lane 2: 1
LOS Indicator for (Serdes Loss of signal) lane 3: 1
Frame Sync error (unexpected k28.5) for lane 3: 1
lane0 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane1 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane2 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane3 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane0 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
lane1 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
lane2 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
lane3 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
CS State TX0: 0b11111111 . It is expected to be 0b00001010
FS State TX0: 0b11111111 . It is expected to be 0b00000101
Couldn't get the link up for device RX: 0; Alarms: 0xfffffffffffffff7L
###################################
###########Device DAC JESD-RX 1 Link Status###########
LOS Indicator for (Serdes Loss of signal) lane 0: 1
Frame Sync error (unexpected k28.5) for lane 0: 1
LOS Indicator for (Serdes Loss of signal) lane 1: 1
Frame Sync error (unexpected k28.5) for lane 1: 1
LOS Indicator for (Serdes Loss of signal) lane 2: 1
Frame Sync error (unexpected k28.5) for lane 2: 1
LOS Indicator for (Serdes Loss of signal) lane 3: 1
Frame Sync error (unexpected k28.5) for lane 3: 1
lane0 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane1 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane2 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane3 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane0 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
lane1 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
lane2 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
lane3 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
CS State TX0: 0b11111111 . It is expected to be 0b00001010
FS State TX0: 0b11111111 . It is expected to be 0b00000101
Couldn't get the link up for device RX: 1; Alarms: 0xfffffffffffffff7L
###################################
SPIA has got control of PLL pages
PLL Pages SPI control relinquished.
MACRO_READY: True
MACRO_ACK: True
MACRO_DONE: True
MACRO_ERROR: True
MACRO_ERROR_IN_OPCODE: True
MACRO_ERROR_OPCODE_NOT_ALLOWED: True
MACRO_ERROR_IN_OPERAND: True
MACRO_ERROR_IN_EXECUTION: True
MACRO_ERROR_OPCODE: 255
MACRO_ERROR_EXTENDED: 65535
MACRO_READY: True
MACRO_ACK: True
MACRO_DONE: True
MACRO_ERROR: True
MACRO_ERROR_IN_OPCODE: True
MACRO_ERROR_OPCODE_NOT_ALLOWED: True
MACRO_ERROR_IN_OPERAND: True
MACRO_ERROR_IN_EXECUTION: True
MACRO_ERROR_OPCODE: 255
MACRO_ERROR_EXTENDED: 65535
TX IQMC: TX-FB loopback selection is in SPI mode. To change to pin, use "AFE.TOP.txIqmcFbLoopbackControl(1)"
#Done executing .. AFE77xx/J58_initial/Alpha_EVM_bringup.py
#End Time 2024-02-15 15:46:01.884000
#Execution Time = 620.049999952 s 
#================ ERRORS:85, WARNINGS:1 ================#
#======
#Executing .. AFE77xx/J58_initial/loopback.py
#Start Time 2024-02-15 15:46:39.417000 
device.writeReg(0x15,0x08)
device.readReg(0x0000004B,0x000000FF)
device.readReg(0x0000004A,0x000000FF)
device.readReg(0x00000048,0x000000FF)
device.writeReg(0x48,0xF7)
device.readReg(0x0000004B,0x000000FF)
device.readReg(0x0000004A,0x000000FF)
device.readReg(0x00000048,0x000000FF)
device.writeReg(0x48,0xFD)
device.readReg(0x0000004B,0x000000FF)
device.readReg(0x0000004A,0x000000FF)
device.readReg(0x00000049,0x000000FF)
device.writeReg(0x49,0xE3)
device.readReg(0x0000004B,0x000000FF)
device.readReg(0x0000004A,0x000000FF)
device.readReg(0x00000049,0x000000FF)
device.writeReg(0x49,0xFF)
device.readReg(0x0000004B,0x000000FF)
device.readReg(0x0000004A,0x000000FF)
device.readReg(0x00000049,0x000000FF)
device.writeReg(0x49,0xFE)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x04)
device.writeReg(0x15,0x04)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x08)
device.readReg(0x00000021,0x000000FF)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x04)
device.writeReg(0x15,0x04)
device.readReg(0x00004687,0x000000FF)
device.readReg(0x00004687,0x000000FF)
device.readReg(0x00004686,0x000000FF)
device.readReg(0x00004686,0x000000FF)
device.writeReg(0x4687,0xFF)
device.writeReg(0x4686,0xFF)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x08)
device.readReg(0x00000021,0x000000FF)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x04)
device.writeReg(0x15,0x04)
device.readReg(0x00004487,0x000000FF)
device.readReg(0x00004487,0x000000FF)
device.readReg(0x00004486,0x000000FF)
device.readReg(0x00004486,0x000000FF)
device.writeReg(0x4487,0xFF)
device.writeReg(0x4486,0xFF)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x08)
device.readReg(0x00000021,0x000000FF)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x04)
device.writeReg(0x15,0x04)
device.readReg(0x00004087,0x000000FF)
device.readReg(0x00004087,0x000000FF)
device.readReg(0x00004086,0x000000FF)
device.readReg(0x00004086,0x000000FF)
device.writeReg(0x4087,0xFF)
device.writeReg(0x4086,0xFF)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x08)
device.readReg(0x00000021,0x000000FF)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x04)
device.writeReg(0x15,0x04)
device.readReg(0x00004287,0x000000FF)
device.readReg(0x00004287,0x000000FF)
device.readReg(0x00004286,0x000000FF)
device.readReg(0x00004286,0x000000FF)
device.writeReg(0x4287,0xFF)
device.writeReg(0x4286,0xFF)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x40)
device.writeReg(0x15,0x40)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x08)
device.readReg(0x00000022,0x000000FF)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x40)
device.readReg(0x00004287,0x000000FF)
device.readReg(0x00004287,0x000000FF)
device.readReg(0x00004286,0x000000FF)
device.readReg(0x00004286,0x000000FF)
device.writeReg(0x4287,0xFF)
device.writeReg(0x4286,0xFF)
device.writeReg(0x15,0x40)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x08)
device.readReg(0x00000022,0x000000FF)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x40)
device.readReg(0x00004087,0x000000FF)
device.readReg(0x00004087,0x000000FF)
device.readReg(0x00004086,0x000000FF)
device.readReg(0x00004086,0x000000FF)
device.writeReg(0x4087,0xFF)
device.writeReg(0x4086,0xFF)
device.writeReg(0x15,0x40)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x08)
device.readReg(0x00000022,0x000000FF)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x40)
device.readReg(0x00004487,0x000000FF)
device.readReg(0x00004487,0x000000FF)
device.readReg(0x00004486,0x000000FF)
device.readReg(0x00004486,0x000000FF)
device.writeReg(0x4487,0xFF)
device.writeReg(0x4486,0xFF)
device.writeReg(0x15,0x40)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x08)
device.readReg(0x00000022,0x000000FF)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x40)
device.readReg(0x00004687,0x000000FF)
device.readReg(0x00004687,0x000000FF)
device.readReg(0x00004686,0x000000FF)
device.readReg(0x00004686,0x000000FF)
device.writeReg(0x4687,0xFF)
device.writeReg(0x4686,0xFF)
device.writeReg(0x15,0x40)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x01)
device.writeReg(0x15,0x01)
device.readReg(0x00000073,0x000000FF)
device.readReg(0x00000072,0x000000FF)
device.writeReg(0x72,0xCF)
device.readReg(0x00000073,0x000000FF)
device.readReg(0x00000072,0x000000FF)
device.writeReg(0x72,0xFC)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x10)
device.readReg(0x00000073,0x000000FF)
device.readReg(0x00000072,0x000000FF)
device.writeReg(0x72,0xCF)
device.readReg(0x00000073,0x000000FF)
device.readReg(0x00000072,0x000000FF)
device.writeReg(0x72,0xFC)
device.writeReg(0x15,0x11)
device.writeReg(0x15,0x01)
device.readReg(0x00000073,0x000000FF)
device.readReg(0x00000072,0x000000FF)
device.writeReg(0x72,0xCF)
device.readReg(0x00000073,0x000000FF)
device.readReg(0x00000072,0x000000FF)
device.writeReg(0x72,0xF0)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x10)
device.readReg(0x00000073,0x000000FF)
device.readReg(0x00000072,0x000000FF)
device.writeReg(0x72,0xCF)
device.readReg(0x00000073,0x000000FF)
device.readReg(0x00000072,0x000000FF)
device.writeReg(0x72,0xF0)
device.writeReg(0x15,0x10)
device.writeReg(0x15,0x00)
###########Device DAC JESD-RX 0 Link Status###########
LOS Indicator for (Serdes Loss of signal) lane 0: 1
Frame Sync error (unexpected k28.5) for lane 0: 1
LOS Indicator for (Serdes Loss of signal) lane 1: 1
Frame Sync error (unexpected k28.5) for lane 1: 1
LOS Indicator for (Serdes Loss of signal) lane 2: 1
Frame Sync error (unexpected k28.5) for lane 2: 1
LOS Indicator for (Serdes Loss of signal) lane 3: 1
Frame Sync error (unexpected k28.5) for lane 3: 1
lane0 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane1 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane2 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane3 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane0 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
lane1 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
lane2 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
lane3 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
CS State TX0: 0b11111111 . It is expected to be 0b00001010
FS State TX0: 0b11111111 . It is expected to be 0b00000101
Couldn't get the link up for device RX: 0; Alarms: 0xfffffffffffffff7L
###################################
###########Device DAC JESD-RX 1 Link Status###########
LOS Indicator for (Serdes Loss of signal) lane 0: 1
Frame Sync error (unexpected k28.5) for lane 0: 1
LOS Indicator for (Serdes Loss of signal) lane 1: 1
Frame Sync error (unexpected k28.5) for lane 1: 1
LOS Indicator for (Serdes Loss of signal) lane 2: 1
Frame Sync error (unexpected k28.5) for lane 2: 1
LOS Indicator for (Serdes Loss of signal) lane 3: 1
Frame Sync error (unexpected k28.5) for lane 3: 1
lane0 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane1 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane2 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane3 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane0 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
lane1 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
lane2 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
lane3 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
CS State TX0: 0b11111111 . It is expected to be 0b00001010
FS State TX0: 0b11111111 . It is expected to be 0b00000101
Couldn't get the link up for device RX: 1; Alarms: 0xfffffffffffffff7L
###################################
#Done executing .. AFE77xx/J58_initial/loopback.py
#End Time 2024-02-15 15:47:13.332000
#Execution Time = 33.9149999619 s 
#================ ERRORS:34, WARNINGS:0 ================#

#======
#Executing .. AFE77xx/J58_initial/setup_J58.py
#Start Time 2024-02-15 16:45:49.937000 
AFE77xxLibraryPG1P1
Automatic reset of fpga will not be supported.
spi - USB Instrument created.
resetDevice
Purge
MPSSE mode set
LMK RegProgrammer - USB Instrument created.
CPLD RegProgrammer - USB Instrument created.
#Done executing .. AFE77xx/J58_initial/setup_J58.py
#End Time 2024-02-15 16:45:55.729000
#Execution Time = 5.79200005531 s 
#================ ERRORS:0, WARNINGS:1 ================#
#======
#Executing .. AFE77xx/J58_initial/devInit_J58.py
#Start Time 2024-02-15 16:46:12.428000 
Version : 0x104204b
Connected to Capture Card
Successfully Loaded the Libraries.
Could not find attribute _logWidget in systemParamClassiGui
Couldn't load iGui
13
#Done executing .. AFE77xx/J58_initial/devInit_J58.py
#End Time 2024-02-15 16:46:53.245000
#Execution Time = 40.8169999123 s 
#================ ERRORS:1, WARNINGS:1 ================#
#======
#Executing .. AFE77xx/J58_initial/Alpha_EVM_bringup.py
#Start Time 2024-02-15 16:47:04.933000 
DONOT_OPEN_Afe77xxPG1p1_FULL - Device registers reset.
chipType: 0xa
chipId: 0x77
chipVersion: 0x11
2T2R1F Number: 0
Valid Configuration: True
laneRateRx: 4915.2
laneRateFb: 4915.2
laneRateTx: 4915.2
2T2R1F Number: 1
Valid Configuration: True
laneRateRx: 4915.2
laneRateFb: 4915.2
laneRateTx: 4915.2
Resetting FPGA.
Version : 0x104204b
Connected to Capture Card
LMK Clock Divider - Device registers reset.
lmk.writeReg(000,0x00000080)
lmk.writeReg(000,0x00000000)
LMK Clock Divider - Device registers reset.
lmk.writeReg(000,0x00000080)
lmk.writeReg(000,0x00000000)
lmk.writeReg(000,0x00000080)
lmk.writeReg(000,0x00000000)
lmk.writeReg(330,0x00000003)
lmk.writeReg(330,0x00000033)
lmk.writeReg(000,0x00000000)
lmk.writeReg(002,0x00000000)
lmk.writeReg(256,0x0000000C)
lmk.writeReg(256,0x0000000C)
lmk.writeReg(256,0x0000000C)
lmk.writeReg(257,0x00000055)
lmk.writeReg(257,0x00000055)
lmk.writeReg(259,0x00000001)
lmk.writeReg(259,0x00000001)
lmk.writeReg(259,0x00000001)
lmk.writeReg(260,0x00000000)
lmk.writeReg(260,0x00000000)
lmk.writeReg(260,0x00000020)
lmk.writeReg(260,0x00000020)
lmk.writeReg(261,0x00000000)
lmk.writeReg(261,0x00000000)
lmk.writeReg(262,0x00000018)
lmk.writeReg(262,0x00000018)
lmk.writeReg(262,0x00000010)
lmk.writeReg(262,0x00000010)
lmk.writeReg(262,0x00000090)
lmk.writeReg(263,0x00000001)
lmk.writeReg(263,0x00000001)
lmk.writeReg(263,0x00000011)
lmk.writeReg(263,0x00000011)
lmk.writeReg(264,0x00000006)
lmk.writeReg(264,0x00000026)
lmk.writeReg(264,0x00000066)
lmk.writeReg(265,0x00000055)
lmk.writeReg(265,0x00000055)
lmk.writeReg(267,0x00000001)
lmk.writeReg(267,0x00000001)
lmk.writeReg(267,0x00000001)
lmk.writeReg(268,0x00000000)
lmk.writeReg(268,0x00000000)
lmk.writeReg(268,0x00000020)
lmk.writeReg(268,0x00000020)
lmk.writeReg(269,0x00000000)
lmk.writeReg(269,0x00000000)
lmk.writeReg(270,0x00000018)
lmk.writeReg(270,0x00000018)
lmk.writeReg(270,0x00000010)
lmk.writeReg(270,0x00000010)
lmk.writeReg(270,0x00000090)
lmk.writeReg(271,0x00000004)
REFCLOCK is used from LMK source, ensure board connections are ok to do the same
lmk.writeReg(271,0x00000004)
lmk.writeReg(271,0x00000014)
lmk.writeReg(271,0x00000014)
lmk.writeReg(272,0x00000008)
lmk.writeReg(272,0x00000008)
lmk.writeReg(272,0x00000008)
lmk.writeReg(273,0x00000055)
lmk.writeReg(273,0x00000055)
lmk.writeReg(275,0x00000000)
lmk.writeReg(275,0x00000000)
lmk.writeReg(275,0x00000000)
lmk.writeReg(276,0x00000000)
lmk.writeReg(276,0x00000000)
lmk.writeReg(276,0x00000000)
lmk.writeReg(276,0x00000000)
lmk.writeReg(277,0x00000000)
lmk.writeReg(277,0x00000000)
lmk.writeReg(278,0x00000011)
lmk.writeReg(278,0x00000011)
lmk.writeReg(278,0x00000019)
lmk.writeReg(278,0x00000019)
lmk.writeReg(278,0x00000099)
lmk.writeReg(279,0x00000000)
lmk.writeReg(279,0x00000000)
lmk.writeReg(279,0x00000000)
lmk.writeReg(279,0x00000000)
lmk.writeReg(280,0x00000018)
lmk.writeReg(280,0x00000018)
lmk.writeReg(280,0x00000018)
lmk.writeReg(281,0x00000055)
lmk.writeReg(281,0x00000055)
lmk.writeReg(283,0x00000000)
lmk.writeReg(283,0x00000000)
lmk.writeReg(283,0x00000000)
lmk.writeReg(284,0x00000000)
lmk.writeReg(284,0x00000000)
lmk.writeReg(284,0x00000020)
lmk.writeReg(284,0x00000020)
lmk.writeReg(285,0x00000000)
lmk.writeReg(285,0x00000000)
lmk.writeReg(286,0x00000011)
lmk.writeReg(286,0x00000011)
lmk.writeReg(286,0x00000019)
lmk.writeReg(286,0x00000019)
lmk.writeReg(286,0x00000099)
lmk.writeReg(287,0x00000000)
lmk.writeReg(287,0x00000000)
lmk.writeReg(287,0x00000000)
lmk.writeReg(287,0x00000000)
lmk.writeReg(288,0x0000000C)
lmk.writeReg(288,0x0000000C)
lmk.writeReg(288,0x0000000C)
lmk.writeReg(289,0x00000055)
lmk.writeReg(289,0x00000055)
lmk.writeReg(291,0x00000000)
lmk.writeReg(291,0x00000000)
lmk.writeReg(291,0x00000000)
lmk.writeReg(292,0x00000000)
lmk.writeReg(292,0x00000000)
lmk.writeReg(292,0x00000000)
lmk.writeReg(292,0x00000000)
lmk.writeReg(293,0x00000000)
lmk.writeReg(293,0x00000000)
lmk.writeReg(294,0x00000011)
lmk.writeReg(294,0x00000011)
lmk.writeReg(294,0x00000019)
lmk.writeReg(294,0x00000019)
lmk.writeReg(294,0x00000099)
lmk.writeReg(295,0x00000001)
lmk.writeReg(295,0x00000001)
lmk.writeReg(295,0x00000011)
lmk.writeReg(295,0x00000011)
lmk.writeReg(296,0x00000008)
lmk.writeReg(296,0x00000008)
lmk.writeReg(296,0x00000008)
lmk.writeReg(297,0x00000055)
lmk.writeReg(297,0x00000055)
lmk.writeReg(299,0x00000000)
lmk.writeReg(299,0x00000000)
lmk.writeReg(299,0x00000000)
lmk.writeReg(300,0x00000000)
lmk.writeReg(300,0x00000000)
lmk.writeReg(300,0x00000000)
lmk.writeReg(300,0x00000000)
lmk.writeReg(301,0x00000000)
lmk.writeReg(301,0x00000000)
lmk.writeReg(302,0x00000011)
lmk.writeReg(302,0x00000011)
lmk.writeReg(302,0x00000019)
lmk.writeReg(302,0x00000019)
lmk.writeReg(302,0x00000099)
lmk.writeReg(303,0x00000000)
lmk.writeReg(303,0x00000000)
lmk.writeReg(303,0x00000000)
lmk.writeReg(303,0x00000000)
lmk.writeReg(304,0x0000000C)
lmk.writeReg(304,0x0000000C)
lmk.writeReg(304,0x0000000C)
lmk.writeReg(305,0x00000055)
lmk.writeReg(305,0x00000055)
lmk.writeReg(307,0x00000000)
lmk.writeReg(307,0x00000000)
lmk.writeReg(307,0x00000000)
lmk.writeReg(308,0x00000000)
lmk.writeReg(308,0x00000000)
lmk.writeReg(308,0x00000020)
lmk.writeReg(308,0x00000020)
lmk.writeReg(309,0x00000000)
lmk.writeReg(309,0x00000000)
lmk.writeReg(310,0x00000019)
lmk.writeReg(310,0x00000019)
lmk.writeReg(310,0x00000011)
lmk.writeReg(310,0x00000011)
lmk.writeReg(310,0x00000091)
lmk.writeReg(311,0x00000001)
lmk.writeReg(311,0x00000001)
lmk.writeReg(311,0x00000001)
lmk.writeReg(311,0x00000001)
lmk.writeReg(312,0x00000000)
lmk.writeReg(312,0x00000000)
lmk.writeReg(312,0x00000020)
lmk.writeReg(313,0x00000003)
lmk.writeReg(313,0x00000003)
lmk.writeReg(315,0x00000000)
lmk.writeReg(314,0x00000003)
lmk.writeReg(317,0x00000008)
lmk.writeReg(316,0x00000000)
lmk.writeReg(318,0x00000003)
lmk.writeReg(319,0x00000000)
lmk.writeReg(319,0x00000000)
lmk.writeReg(319,0x00000000)
lmk.writeReg(319,0x00000000)
lmk.writeReg(320,0x00000006)
lmk.writeReg(320,0x00000004)
lmk.writeReg(320,0x00000000)
lmk.writeReg(320,0x00000000)
lmk.writeReg(320,0x00000000)
lmk.writeReg(320,0x00000000)
lmk.writeReg(320,0x00000000)
lmk.writeReg(320,0x00000000)
lmk.writeReg(321,0x00000000)
lmk.writeReg(321,0x00000000)
lmk.writeReg(321,0x00000000)
lmk.writeReg(321,0x00000000)
lmk.writeReg(321,0x00000000)
lmk.writeReg(321,0x00000000)
lmk.writeReg(321,0x00000000)
lmk.writeReg(321,0x00000000)
lmk.writeReg(322,0x00000000)
lmk.writeReg(323,0x00000092)
lmk.writeReg(323,0x00000092)
lmk.writeReg(323,0x00000092)
lmk.writeReg(323,0x00000092)
lmk.writeReg(323,0x00000092)
lmk.writeReg(323,0x00000092)
lmk.writeReg(323,0x00000012)
lmk.writeReg(324,0x00000001)
lmk.writeReg(324,0x00000003)
lmk.writeReg(324,0x00000007)
lmk.writeReg(324,0x0000000F)
lmk.writeReg(324,0x0000001F)
lmk.writeReg(324,0x0000003F)
lmk.writeReg(324,0x0000007F)
lmk.writeReg(324,0x000000FF)
lmk.writeReg(326,0x00000018)
lmk.writeReg(326,0x00000018)
lmk.writeReg(326,0x00000018)
lmk.writeReg(326,0x00000010)
lmk.writeReg(326,0x00000010)
lmk.writeReg(326,0x00000010)
lmk.writeReg(327,0x0000003A)
lmk.writeReg(327,0x0000003A)
lmk.writeReg(327,0x0000001A)
lmk.writeReg(327,0x0000001A)
lmk.writeReg(328,0x00000002)
lmk.writeReg(328,0x00000002)
lmk.writeReg(329,0x00000042)
lmk.writeReg(329,0x00000042)
lmk.writeReg(329,0x00000042)
lmk.writeReg(332,0x00000000)
lmk.writeReg(331,0x00000016)
lmk.writeReg(331,0x00000016)
lmk.writeReg(331,0x00000016)
lmk.writeReg(331,0x00000016)
lmk.writeReg(331,0x00000016)
lmk.writeReg(331,0x00000016)
lmk.writeReg(333,0x00000000)
lmk.writeReg(334,0x00000000)
lmk.writeReg(334,0x000000C0)
lmk.writeReg(335,0x0000007F)
lmk.writeReg(336,0x00000003)
lmk.writeReg(336,0x00000003)
lmk.writeReg(336,0x00000003)
lmk.writeReg(336,0x00000003)
lmk.writeReg(336,0x00000003)
lmk.writeReg(336,0x00000043)
lmk.writeReg(338,0x00000000)
lmk.writeReg(337,0x00000002)
lmk.writeReg(340,0x00000078)
lmk.writeReg(339,0x00000000)
lmk.writeReg(342,0x0000007D)
lmk.writeReg(341,0x00000000)
lmk.writeReg(344,0x00000096)
lmk.writeReg(343,0x00000000)
lmk.writeReg(346,0x00000000)
lmk.writeReg(345,0x00000006)
lmk.writeReg(347,0x000000D4)
lmk.writeReg(347,0x000000D4)
lmk.writeReg(347,0x000000D4)
lmk.writeReg(347,0x000000D4)
lmk.writeReg(349,0x00000000)
lmk.writeReg(348,0x00000020)
lmk.writeReg(350,0x00000000)
lmk.writeReg(350,0x00000000)
lmk.writeReg(351,0x0000000B)
lmk.writeReg(351,0x0000000B)
lmk.writeReg(353,0x00000001)
lmk.writeReg(352,0x00000000)
lmk.writeReg(354,0x0000005C)
lmk.writeReg(354,0x0000005C)
lmk.writeReg(354,0x00000044)
lmk.writeReg(354,0x00000044)
lmk.writeReg(357,0x0000000C)
lmk.writeReg(356,0x00000000)
lmk.writeReg(355,0x00000000)
lmk.writeReg(358,0x00000000)
lmk.writeReg(360,0x0000000C)
lmk.writeReg(359,0x00000000)
lmk.writeReg(358,0x00000000)
lmk.writeReg(361,0x00000058)
lmk.writeReg(361,0x00000058)
lmk.writeReg(361,0x00000058)
lmk.writeReg(361,0x00000058)
lmk.writeReg(363,0x00000000)
lmk.writeReg(362,0x00000020)
lmk.writeReg(364,0x00000000)
lmk.writeReg(364,0x00000000)
lmk.writeReg(365,0x00000000)
lmk.writeReg(365,0x00000000)
lmk.writeReg(366,0x00000013)
lmk.writeReg(366,0x00000013)
lmk.writeReg(380,0x00000015)
lmk.writeReg(381,0x0000000F)
Version : 0x104204b
Connected to Capture Card
Fuse farm load autoload done successful
No autload error
Purge
Purge
MACRO_READY: True
MACRO_ACK: True
MACRO_DONE: True
MACRO_ERROR: False
Purge
MACRO_READY: True
MACRO_ACK: True
MACRO_DONE: True
MACRO_ERROR: False
MACRO_READY: True
MACRO_ACK: True
MACRO_DONE: True
MACRO_ERROR: False
SPIA has got control of PLL pages
pll0: True; LO Frequency: 4849.86
pll1: True; LO Frequency: 2949.12
PLL Pages SPI control relinquished.
FB DSA 4.9G Band
Purge
Purge
Purge
*TX IQMC Patch Apply*
SPIA has got control of PLL pages
PLL Pages SPI control relinquished.
FW_VERSION=0x11119e
attack_value: 2899.74593284
decay_value: 1829.61599345
attack_value: 3253.56844943
decay_value: 2052.86290894
attack_value: 2899.74593284
decay_value: 1829.61599345
attack_value: 3253.56844943
decay_value: 2052.86290894
SPIA has got control of PLL pages
PLL Pages SPI control relinquished.
Sysref to RX AB, Read: 3; expected: 3
Sysref to RX CD, Read: 3; expected: 3
Sysref to FB A, Read: 1; expected: 1
Sysref to FB D, Read: 1; expected: 1
Sysref to TX AB, Read: 255; expected: 7
Sysref to TX CD, Read: 255; expected: 7
Digital Clock, Read: True; expected: 1
Sysref to Digital, Read: True; expected: 1
Sysref to Analog, Read: 65535; expected: 7
lmk.writeReg(262,0x000000F0)
###########Device DAC JESD-RX 0 Link Status###########
LOS Indicator for (Serdes Loss of signal) lane 0: 1
Frame Sync error (unexpected k28.5) for lane 0: 1
LOS Indicator for (Serdes Loss of signal) lane 1: 1
Frame Sync error (unexpected k28.5) for lane 1: 1
LOS Indicator for (Serdes Loss of signal) lane 2: 1
Frame Sync error (unexpected k28.5) for lane 2: 1
LOS Indicator for (Serdes Loss of signal) lane 3: 1
Frame Sync error (unexpected k28.5) for lane 3: 1
lane0 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane1 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane2 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane3 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane0 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
lane1 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
lane2 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
lane3 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
CS State TX0: 0b11111111 . It is expected to be 0b00001010
FS State TX0: 0b11111111 . It is expected to be 0b00000101
Couldn't get the link up for device RX: 0; Alarms: 0xfffffffffffffff7L
###################################
lmk.writeReg(262,0x000000F1)
lmk.writeReg(262,0x000000F0)
###########Device DAC JESD-RX 1 Link Status###########
LOS Indicator for (Serdes Loss of signal) lane 0: 1
Frame Sync error (unexpected k28.5) for lane 0: 1
LOS Indicator for (Serdes Loss of signal) lane 1: 1
Frame Sync error (unexpected k28.5) for lane 1: 1
LOS Indicator for (Serdes Loss of signal) lane 2: 1
Frame Sync error (unexpected k28.5) for lane 2: 1
LOS Indicator for (Serdes Loss of signal) lane 3: 1
Frame Sync error (unexpected k28.5) for lane 3: 1
lane0 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane1 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane2 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane3 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane0 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
lane1 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
lane2 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
lane3 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
CS State TX0: 0b11111111 . It is expected to be 0b00001010
FS State TX0: 0b11111111 . It is expected to be 0b00000101
Couldn't get the link up for device RX: 1; Alarms: 0xfffffffffffffff7L
###################################
lmk.writeReg(262,0x000000F1)
lmk.writeReg(262,0x000000F0)
lmk.writeReg(262,0x000000F1)
###########Device DAC JESD-RX 0 Link Status###########
LOS Indicator for (Serdes Loss of signal) lane 0: 1
Frame Sync error (unexpected k28.5) for lane 0: 1
LOS Indicator for (Serdes Loss of signal) lane 1: 1
Frame Sync error (unexpected k28.5) for lane 1: 1
LOS Indicator for (Serdes Loss of signal) lane 2: 1
Frame Sync error (unexpected k28.5) for lane 2: 1
LOS Indicator for (Serdes Loss of signal) lane 3: 1
Frame Sync error (unexpected k28.5) for lane 3: 1
lane0 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane1 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane2 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane3 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane0 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
lane1 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
lane2 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
lane3 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
CS State TX0: 0b11111111 . It is expected to be 0b00001010
FS State TX0: 0b11111111 . It is expected to be 0b00000101
Couldn't get the link up for device RX: 0; Alarms: 0xfffffffffffffff7L
###################################
###########Device DAC JESD-RX 1 Link Status###########
LOS Indicator for (Serdes Loss of signal) lane 0: 1
Frame Sync error (unexpected k28.5) for lane 0: 1
LOS Indicator for (Serdes Loss of signal) lane 1: 1
Frame Sync error (unexpected k28.5) for lane 1: 1
LOS Indicator for (Serdes Loss of signal) lane 2: 1
Frame Sync error (unexpected k28.5) for lane 2: 1
LOS Indicator for (Serdes Loss of signal) lane 3: 1
Frame Sync error (unexpected k28.5) for lane 3: 1
lane0 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane1 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane2 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane3 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane0 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
lane1 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
lane2 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
lane3 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
CS State TX0: 0b11111111 . It is expected to be 0b00001010
FS State TX0: 0b11111111 . It is expected to be 0b00000101
Couldn't get the link up for device RX: 1; Alarms: 0xfffffffffffffff7L
###################################
SPIA has got control of PLL pages
PLL Pages SPI control relinquished.
MACRO_READY: True
MACRO_ACK: True
MACRO_DONE: True
MACRO_ERROR: True
MACRO_ERROR_IN_OPCODE: True
MACRO_ERROR_OPCODE_NOT_ALLOWED: True
MACRO_ERROR_IN_OPERAND: True
MACRO_ERROR_IN_EXECUTION: True
MACRO_ERROR_OPCODE: 255
MACRO_ERROR_EXTENDED: 65535
MACRO_READY: True
MACRO_ACK: True
MACRO_DONE: True
MACRO_ERROR: True
MACRO_ERROR_IN_OPCODE: True
MACRO_ERROR_OPCODE_NOT_ALLOWED: True
MACRO_ERROR_IN_OPERAND: True
MACRO_ERROR_IN_EXECUTION: True
MACRO_ERROR_OPCODE: 255
MACRO_ERROR_EXTENDED: 65535
TX IQMC: TX-FB loopback selection is in SPI mode. To change to pin, use "AFE.TOP.txIqmcFbLoopbackControl(1)"
#Done executing .. AFE77xx/J58_initial/Alpha_EVM_bringup.py
#End Time 2024-02-15 16:57:20.246000
#Execution Time = 615.312999964 s 
#================ ERRORS:83, WARNINGS:1 ================#
#======
#Executing .. AFE77xx/J58_initial/loopback.py
#Start Time 2024-02-15 16:58:21.842000 
device.writeReg(0x15,0x08)
device.readReg(0x0000004B,0x000000FF)
device.readReg(0x0000004A,0x000000FF)
device.readReg(0x00000048,0x000000FF)
device.writeReg(0x48,0xF7)
device.readReg(0x0000004B,0x000000FF)
device.readReg(0x0000004A,0x000000FF)
device.readReg(0x00000048,0x000000FF)
device.writeReg(0x48,0xFD)
device.readReg(0x0000004B,0x000000FF)
device.readReg(0x0000004A,0x000000FF)
device.readReg(0x00000049,0x000000FF)
device.writeReg(0x49,0xE3)
device.readReg(0x0000004B,0x000000FF)
device.readReg(0x0000004A,0x000000FF)
device.readReg(0x00000049,0x000000FF)
device.writeReg(0x49,0xFF)
device.readReg(0x0000004B,0x000000FF)
device.readReg(0x0000004A,0x000000FF)
device.readReg(0x00000049,0x000000FF)
device.writeReg(0x49,0xFE)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x04)
device.writeReg(0x15,0x04)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x08)
device.readReg(0x00000021,0x000000FF)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x04)
device.writeReg(0x15,0x04)
device.readReg(0x00004687,0x000000FF)
device.readReg(0x00004687,0x000000FF)
device.readReg(0x00004686,0x000000FF)
device.readReg(0x00004686,0x000000FF)
device.writeReg(0x4687,0xFF)
device.writeReg(0x4686,0xFF)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x08)
device.readReg(0x00000021,0x000000FF)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x04)
device.writeReg(0x15,0x04)
device.readReg(0x00004487,0x000000FF)
device.readReg(0x00004487,0x000000FF)
device.readReg(0x00004486,0x000000FF)
device.readReg(0x00004486,0x000000FF)
device.writeReg(0x4487,0xFF)
device.writeReg(0x4486,0xFF)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x08)
device.readReg(0x00000021,0x000000FF)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x04)
device.writeReg(0x15,0x04)
device.readReg(0x00004087,0x000000FF)
device.readReg(0x00004087,0x000000FF)
device.readReg(0x00004086,0x000000FF)
device.readReg(0x00004086,0x000000FF)
device.writeReg(0x4087,0xFF)
device.writeReg(0x4086,0xFF)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x08)
device.readReg(0x00000021,0x000000FF)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x04)
device.writeReg(0x15,0x04)
device.readReg(0x00004287,0x000000FF)
device.readReg(0x00004287,0x000000FF)
device.readReg(0x00004286,0x000000FF)
device.readReg(0x00004286,0x000000FF)
device.writeReg(0x4287,0xFF)
device.writeReg(0x4286,0xFF)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x40)
device.writeReg(0x15,0x40)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x08)
device.readReg(0x00000022,0x000000FF)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x40)
device.readReg(0x00004287,0x000000FF)
device.readReg(0x00004287,0x000000FF)
device.readReg(0x00004286,0x000000FF)
device.readReg(0x00004286,0x000000FF)
device.writeReg(0x4287,0xFF)
device.writeReg(0x4286,0xFF)
device.writeReg(0x15,0x40)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x08)
device.readReg(0x00000022,0x000000FF)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x40)
device.readReg(0x00004087,0x000000FF)
device.readReg(0x00004087,0x000000FF)
device.readReg(0x00004086,0x000000FF)
device.readReg(0x00004086,0x000000FF)
device.writeReg(0x4087,0xFF)
device.writeReg(0x4086,0xFF)
device.writeReg(0x15,0x40)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x08)
device.readReg(0x00000022,0x000000FF)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x40)
device.readReg(0x00004487,0x000000FF)
device.readReg(0x00004487,0x000000FF)
device.readReg(0x00004486,0x000000FF)
device.readReg(0x00004486,0x000000FF)
device.writeReg(0x4487,0xFF)
device.writeReg(0x4486,0xFF)
device.writeReg(0x15,0x40)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x08)
device.readReg(0x00000022,0x000000FF)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x40)
device.readReg(0x00004687,0x000000FF)
device.readReg(0x00004687,0x000000FF)
device.readReg(0x00004686,0x000000FF)
device.readReg(0x00004686,0x000000FF)
device.writeReg(0x4687,0xFF)
device.writeReg(0x4686,0xFF)
device.writeReg(0x15,0x40)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x01)
device.writeReg(0x15,0x01)
device.readReg(0x00000073,0x000000FF)
device.readReg(0x00000072,0x000000FF)
device.writeReg(0x72,0xCF)
device.readReg(0x00000073,0x000000FF)
device.readReg(0x00000072,0x000000FF)
device.writeReg(0x72,0xFC)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x10)
device.readReg(0x00000073,0x000000FF)
device.readReg(0x00000072,0x000000FF)
device.writeReg(0x72,0xCF)
device.readReg(0x00000073,0x000000FF)
device.readReg(0x00000072,0x000000FF)
device.writeReg(0x72,0xFC)
device.writeReg(0x15,0x11)
device.writeReg(0x15,0x01)
device.readReg(0x00000073,0x000000FF)
device.readReg(0x00000072,0x000000FF)
device.writeReg(0x72,0xCF)
device.readReg(0x00000073,0x000000FF)
device.readReg(0x00000072,0x000000FF)
device.writeReg(0x72,0xF0)
device.writeReg(0x15,0x00)
device.writeReg(0x15,0x10)
device.readReg(0x00000073,0x000000FF)
device.readReg(0x00000072,0x000000FF)
device.writeReg(0x72,0xCF)
device.readReg(0x00000073,0x000000FF)
device.readReg(0x00000072,0x000000FF)
device.writeReg(0x72,0xF0)
device.writeReg(0x15,0x10)
device.writeReg(0x15,0x00)
###########Device DAC JESD-RX 0 Link Status###########
LOS Indicator for (Serdes Loss of signal) lane 0: 1
Frame Sync error (unexpected k28.5) for lane 0: 1
LOS Indicator for (Serdes Loss of signal) lane 1: 1
Frame Sync error (unexpected k28.5) for lane 1: 1
LOS Indicator for (Serdes Loss of signal) lane 2: 1
Frame Sync error (unexpected k28.5) for lane 2: 1
LOS Indicator for (Serdes Loss of signal) lane 3: 1
Frame Sync error (unexpected k28.5) for lane 3: 1
lane0 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane1 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane2 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane3 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane0 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
lane1 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
lane2 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
lane3 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
CS State TX0: 0b11111111 . It is expected to be 0b00001010
FS State TX0: 0b11111111 . It is expected to be 0b00000101
Couldn't get the link up for device RX: 0; Alarms: 0xfffffffffffffff7L
###################################
###########Device DAC JESD-RX 1 Link Status###########
LOS Indicator for (Serdes Loss of signal) lane 0: 1
Frame Sync error (unexpected k28.5) for lane 0: 1
LOS Indicator for (Serdes Loss of signal) lane 1: 1
Frame Sync error (unexpected k28.5) for lane 1: 1
LOS Indicator for (Serdes Loss of signal) lane 2: 1
Frame Sync error (unexpected k28.5) for lane 2: 1
LOS Indicator for (Serdes Loss of signal) lane 3: 1
Frame Sync error (unexpected k28.5) for lane 3: 1
lane0 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane1 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane2 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane3 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); 
lane0 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
lane1 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
lane2 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
lane3 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; 
CS State TX0: 0b11111111 . It is expected to be 0b00001010
FS State TX0: 0b11111111 . It is expected to be 0b00000101
Couldn't get the link up for device RX: 1; Alarms: 0xfffffffffffffff7L
###################################
#Done executing .. AFE77xx/J58_initial/loopback.py
#End Time 2024-02-15 16:58:53.835000
#Execution Time = 31.9930000305 s 
#================ ERRORS:34, WARNINGS:0 ================#