- Ask a related questionWhat is a related question?A related question is a question created from another question. When the related question is created, it will be automatically linked to the original question.
Hi expert,
Customer measured Rx EVM of AFE7799 on their board and got over 2.5%. Would you please advise possible methods to improve Rx EVM?
|
256QAM |
SG input power (dBm) |
||||||||
|
-50 |
-45 |
-40 |
-35 |
-30 |
-25 |
-20 |
|
||
|
RXATT |
10 |
5.75 |
4.23 |
3.05 |
2.75 |
2.49 |
3.3 |
3.371 |
|
Thanks,
Allan
Hi Kang,
Please see below comments;
Thanks,
Allan
Customer to please advise the two actions above
Per our discussion, we will do the following:
Thank you.
Hi Kang,
Customer originally use -50Mhz to -30Mhz bandwidth from LO and now move to -40Mhz to -20Mhz. The EVM improved from -7% to -2%.
They are still doing test to enable RXTDD 2us before Rx.
In the meantime, customer also tried to use loopback followed your steps. Some questions,
Q1. how to boot up the AFE7769EVM using the configCustom2_4849.86 configuration text file in Latte?
Customer add loopback script directly into Latte, and show errors and sync failed.
Q2: please advise what might goes wrong when customer implement the loopback script?
Here is the test setup and result by plugging SG directly into the spectrum analyzer 256QAM analysis to see the raw EVM%.
Q3: customer is TDD system, but for loopback, want to clarify shall we use FDD instead?
Thanks,
Allan
Hi Allan,
Please advise which plot is below: is it loopback or is it directly captured from the RX? The EVM% is very good and less than 2%. We would like to double check how did the customer arrive to this?
Regarding your other questions:
Customer originally use -50Mhz to -30Mhz bandwidth from LO and now move to -40Mhz to -20Mhz. The EVM improved from -7% to -2%.
Could the customer please double check if the RX interface rate is currently set to 122.88MSPS. If the interface rate is at 122.88MSPS, the DDC bandwidth is only 100MHz (i.e. 122.88MSPS*80%). Therefore, the utilization of the -50MHz at the band edge may be pushing towards the edge of the DDC filter.
They are still doing test to enable RXTDD 2us before Rx.
For now, please ensure RXTDD pin is always in logic HI in FDD mode so we can have the RX signal chain enabled all the time. This will prevent additional variable introduced to the EVM% from the RX signal chain switching characteristics.
Q1. how to boot up the AFE7769EVM using the configCustom2_4849.86 configuration text file in Latte?
We are currently looking into a native boot of the configuration file sequence for you. We will upload the code once we find it.
Q2: please advise what might goes wrong when customer implement the loopback script?
Here is the test setup and result by plugging SG directly into the spectrum analyzer 256QAM analysis to see the raw EVM%.
We are still working on this and will get back to you.
Q3: customer is TDD system, but for loopback, want to clarify shall we use FDD instead?
Please keep RXTDD pin is always in logic HI in FDD mode for now to prevent additional transient variables.
Hi Kang,
The 0.57% EVM is just a directly captured from the RX as a good reference to approve the Rx signal is good.
RX interface rate is set to 122.88MSPS.
One thing want to correct is the test did yesterday the EVM improved from -7% to -2% only happened once.
Customer did some further different tests shifting the carrier but don't see EVM much different.
p.s. SG to AFE7799 Rx and RxTDD set to 10dB.
1. Start PRB0 and RXTDD is TDD mode
2. Start PRB0 and RXTDD is always On in FDD mode.
3. Start PRB25 and RXTDD is TDD mode
4. Start PRB111 and RXTDD is TDD mode
Also wondering, is there any possible HW design e.g. power, clocks may impact the Rx EVM as well? If so, could you please point out something for customer to check?
Regards,
Allan
Kang,
Customer clarified the test history. EVM was good by changing the RF start trigger timing from 1588 application to DU emulator 1pps signal. But the EVM 2% was the best case and hard to duplicate at the same environment.
p.s. in the previous tests that SG to AFE7799 Rx and RxTDD set to 10dB.
Thanks,
Allan
Hi Kang,
could you please advise how the 1pps signal is connected to the AFE7799?
After clarifying, please see updated test setup,
Regards,
Allan
Hi Allan,
After clarifying, please see updated test setup,
In regards to the diagram above, from TI's perspective, we will need clarification on the RF timer sync timing by 1588 application to the RXTDD pins for TDD control.
I would like to recommend Tzuchung to override the RXTDD to have the RX chain always enabled, as requested on Jan 29th, 2024.
Please use overrideTdd(int fd = 0, int overrideEN = 1, rxTdd = 3, fbtTdd = don't care, txTdd = don't care) function to always enable the RX chain. The impact from the RF timer sync timing by 1588 applications should no longer be a variable.
Once the 1588 applications to the AFE7799 device RXTDD control is no longer a variable, please report back the EVM%. The best EVM% will be the current best theoretical EVM%.
-Kang
Dear Kang:
Question 1:
We want to confirm configCustom2_4849p86.txt provided by us need to any modification or not for RX EVM improvement? Because all test and measurement depend on AFE7799 configuration is valid without error.
Question 2:
If we hope to use the “void overrideTdd” function to do the test, we must translate overrideTdd function to txt mode.Beside we have done EVM measurement by FPGA always configure RXATT is High. So TI want to measure the EVM again by overrideTdd function again or not?
HI Serken:
we answer and confirmations are on the below. Please check and response.
1.Which FPGA board you are using for TI FPGA? TWS14J56
2.Are your running setup and devinit before the bringup file? setup and devinit files are specific to FPGA board versions.
Latee procedures should be on the below. If the below procedures are not correct, please clarify us. Thanks a lot.
a. Run devinit_j58.py
b. Setup_j58.py
c. Alpha_EVM_bringup.py
d. Loopback.py
3.confirm the overwritetdd.txt setup.
we plan to use upper setup to run overwritetdd.txt by the below procedures. If procedures are not correct, please clarify us.
a. FPGA ARM CPU use configCustom2_4849p86.txt to communicate with AFE7799 by SPI interface.
b. FPGA ARM CPU use txt to communicate with AFE7799 by SPI interface.
4. confirm the loopback.txt setup
a. Rx1 and Tx1 porting mapping
Rx1 is right picture 1RxB or not?
Tx1 is right picture 1TX or not?
b. loopback.txt can run at TDD mode or not?
Alpha configCustom2_4849p86.txt file is TDD mode. Loopback.txt can run at TDD mode or not? If AFE7799 can not run at TDD mode, how to force 7799 at TDD mode before run loopback.txt
c. procedures confirm
If loopback.txt can run after tdd mode configCustom2_4849p86.txt, please confirm below procedures are correct or not?
c.1 FPGA ARM CPU use configCustom2_4849p86.txt to communicate with AFE7799 by SPI interface
c.2 FPGA ARM CPU use loopback.txt to communicate with AFE7799 by SPI interface
Hi Serkan,
Which FPGA board you are using for TI FPGA?
Originally they used 'J56EVM to test but they also have 'J58EVM on hand and in order to make us easier to debug/compare and to have as small difference as with your provided script files.
1) If the TI FPGA board is TSW14J58, run setup first. Then follow the bringup steps for TI FPGA.
Here are some result from their test with 'J58EVM with AFE7769EVM followed your suggested steps. But showing some error and need your help to advise.
Power Supply 5.5V (Fail) ：JESD204 sync failure, K code sync failure.
a. Setup_j58.py
b. Run devinit_j58.py
c. Alpha_EVM_bringup.py
d. Loopback.py
Not sure if the supply matters, they did another test with 6V.
Power Supply 6V (Fail) : JESD204 sync failure, K code sync failure.
a. Setup_j58.py
b. Run devinit_j58.py
c. Alpha_EVM_bringup.py
d. Loopback.py
Switch_A_a_B_6V_latte_infor.txt
Both two tests stop at the same stage. The error message:
LOS Indicator for (Serdes Loss of signal) lane 0: 1
Frame Sync error (unexpected k28.5) for lane 0: 1
LOS Indicator for (Serdes Loss of signal) lane 1: 1
Frame Sync error (unexpected k28.5) for lane 1: 1
LOS Indicator for (Serdes Loss of signal) lane 2: 1
Frame Sync error (unexpected k28.5) for lane 2: 1
LOS Indicator for (Serdes Loss of signal) lane 3: 1
Frame Sync error (unexpected k28.5) for lane 3: 1
lane0 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state);
lane1 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state);
lane2 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state);
lane3 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state);
lane0 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error;
lane1 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error;
lane2 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error;
lane3 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error;
CS State TX0: 0b11111111 . It is expected to be 0b00001010
FS State TX0: 0b11111111 . It is expected to be 0b00000101
Couldn't get the link up for device RX: 0; Alarms: 0xfffffffffffffff7L
I would like to recommend Tzuchung to override the RXTDD to have the RX chain always enabled, as requested on Jan 29th, 2024.
Per Kang's advice, they had done a test to override the RXTDD by FPGA GPIO instead of using overrideTdd() function.
Start PRB0 and RXTDD is always On in FDD mode.
Not sure what might be difference but they will try with overrideTdd() function again and update the result.
Thanks,
Allan
Hi Kang, Serkan,
Customer optimized the Keysight DU emulator environment to do the different input power EVM test. The test setup is on the below.
https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/220/UL-256QAM-EVM_5F00_AFE7799_5F00_RX_5F00_input.7z
Below was UL 256Q EVM test data comparison from different input power measurement points by Keysight generator and SG.
When measured at AFE input, the range of amplitude is -25dBm to -45dBm and expect to see -55dBm to -75dBm at LNA.
From the result, EVM is still over 3% with -60dBm after LNA.
Regards,
Allan
Hi Serkan,
Finally, we had setup loopback successfully using brand new AFE77xxEVM C version + TSW14J58EVM but the noise floor seems quite high so 256QAM can't be demodulated. Could you please advise what can we do?
1. loopback without any signal. the noise floor is about -12dBm
2. loopback with single tone
3. loopback with 5G NR TM3.1a 256Q but failed to demodulation.
p.s. SG to SA directly without through EVMs. ACLR is good about -53/-54dBc. (need to below -45dBc)
Regards,
Allan
Allan,
The input and output signal may be digitally saturated. Please ask the customer team to refer to the AFE7799 datasheet, section 8.6 to understand the RX line-up and full-scale input power to ensure proper attenuation is set to not saturate the input.
The same applies to the TX output
Kang,
loopback without any signal. the noise floor is about -12dBm
This is a loopback setup without input signal and AFE Tx connect directly to the SA. So we thought the Rx input power should be no problem but don't know why output noise floor seems quite high and over the spec. Anything else that we can check/adjust?
Regards,
Allan
