AFE7900EVM: JESD204B communication link establish between AFE7900EVM and VC707 EVM boards

Tool/software:

Hello,

I am trying to establish JESD204B communication link between VC707 and AFE7900 EVM board for my project. I followed AFE79xx SPI Bring up Guide with Xilinx FPGAs user guide. Tried to pass AFE7900 and LMK register values via SPI protocol, connection was not established and I enable debug mode. I am not getting SCK_O signal from AXI Quad SPI IP core. What could be the reason for not getting serial clock signal. Is there any code modification require for this setup from vitis side. Used clock frequency was 40MHz. Here I enclosed BD and ILA  images.

Thanks